altera cycloneII 2c35 verilog code development and testing DDR, with simulation waveform.

DDR_check
.........\constraints_out.txt
.........\ddr.bsf
.........\ddr.v
.........\ddr_auk_ddr_clk_gen.v
.........\ddr_auk_ddr_datapath.v
.........\ddr_auk_ddr_dqs_group.v
.........\ddr_auk_ddr_sdram.v
.........\ddr_bb.v
.........\DDR_check.qpf
.........\DDR_check.v
.........\DDR_check_1.v
.........\DDR_check_2.v
.........\DDR_check_3.v
.........\DDR_check_4.v
.........\DDR_check_5.v
.........\DDR_check_6.v
.........\DDR_check_7.v
.........\DDR_check_8.v
.........\ddr_ddr_settings.txt
.........\ddr_example_driver.v
.........\ddr_extraction_data.txt
.........\ddr_extraction_log.txt
.........\ddr_extraction_log2.txt
.........\ddr_pll_cycloneii.bsf
.........\ddr_pll_cycloneii.v
.........\ddr_pll_cycloneii_bb.v
.........\ddr_pll_cycloneii_wave0.jpg
.........\ddr_post_summary.txt
.........\ddr_pre_compile_ddr_timing_summary.txt
.........\estimated_data.txt
.........\stp1.stp
.........\stp2.stp

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