Introduction - If you have any usage issues, please Google them yourself
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
ENTITY fpq IS
PORT(clk:IN STD_LOGIC
clk_out:OUT STD_LOGIC)
END fpq
ARCHITECTURE hh OF fpq IS
CONSTANT m : INTEGER:= 5
SIGNAL tmp:STD_LOGIC
BEGIN
PROCESS(clk,tmp)
VARIABLE cout :INTEGER := 0