Including 3:8 decoder, the D flip-flop composed of 8-bit registers, the 8-bit multiplier, 41 multiplexer selector.

8位乘法器\multiply.jpg
.........\multiply_8_test.v
38译码器\decoder.jpg
........\decoder.v
........\decoder_test.v
41多路选择器\selection.jpg
............\selection.v
............\selection_test.v
D触发器组成的8位寄存器\register.jpg
......................\register.v
......................\stimulate_8_Register.v
8位乘法器
38译码器
41多路选择器
D触发器组成的8位寄存器

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