Adder 32 Verilog hdl

add32\add32.fit.rpt
.....\add32.fit.summary
.....\add32.flow.rpt
.....\add32.map.rpt
.....\add32.map.summary
.....\add32.qpf
.....\add32.qsf
.....\add32.v
.....\add32_TB.v
.....\db\add32.cbx.xml
.....\..\add32.cmp.bpm
.....\..\add32.cmp.cdb
.....\..\add32.cmp.hdb
.....\..\add32.cmp.logdb
.....\..\add32.cmp.rdb
.....\..\add32.cmp_merge.kpt
.....\..\add32.db_info
.....\..\add32.fit.qmsg
.....\..\add32.hier_info
.....\..\add32.hif
.....\..\add32.lpc.html
.....\..\add32.lpc.rdb
.....\..\add32.lpc.txt
.....\..\add32.map.bpm
.....\..\add32.map.cdb
.....\..\add32.map.hdb
.....\..\add32.map.kpt
.....\..\add32.map.logdb
.....\..\add32.map.qmsg
.....\..\add32.map_bb.cdb
.....\..\add32.map_bb.hdb
.....\..\add32.map_bb.logdb
.....\..\add32.pre_map.cdb
.....\..\add32.pre_map.hdb
.....\..\add32.rtlv.hdb
.....\..\add32.rtlv_sg.cdb
.....\..\add32.rtlv_sg_swap.cdb
.....\..\add32.sgdiff.cdb
.....\..\add32.sgdiff.hdb
.....\..\add32.sld_design_entry.sci
.....\..\add32.sld_design_entry_dsc.sci
.....\..\add32.smart_action.txt
.....\..\add32.syn_hier_info
.....\..\add32.tis_db_list.ddb
.....\..\add32.tmw_info
.....\..\logic_util_heursitic.dat
.....\incremental_db\compiled_partitions\add32.db_info
.....\..............\...................\add32.root_partition.map.cdb
.....\..............\...................\add32.root_partition.map.dpi
.....\..............\...................\add32.root_partition.map.hbdb.cdb
.....\..............\...................\add32.root_partition.map.hbdb.hb_info
.....\..............\...................\add32.root_partition.map.hbdb.hdb
.....\..............\...................\add32.root_partition.map.hbdb.sig
.....\..............\...................\add32.root_partition.map.hdb
.....\..............\...................\add32.root_partition.map.kpt
.....\..............\README
.....\..............\compiled_partitions
.....\db
.....\incremental_db
add32

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