Fpga-based uart design, including the CPU interface design

RTL\CPU_IF.VHD
...\FIFO\FIFO_8bitx2\blk_ram\blk_mem_8bitx2\doc\blk_mem_gen_ds512.pdf
...\....\...........\.......\..............\...\blk_mem_gen_v6_1_vinfo.html
...\....\...........\.......\blk_mem_8bitx2.asy
...\....\...........\.......\blk_mem_8bitx2.gise
...\....\...........\.......\blk_mem_8bitx2.ncf
...\....\...........\.......\blk_mem_8bitx2.ngc
...\....\...........\.......\blk_mem_8bitx2.vhd
...\....\...........\.......\blk_mem_8bitx2.vho
...\....\...........\.......\blk_mem_8bitx2.xco
...\....\...........\.......\blk_mem_8bitx2.xise
...\....\...........\.......\blk_mem_8bitx2_flist.txt
...\....\...........\.......\blk_mem_8bitx2_xmdf.tcl
...\....\...........\.......\blk_mem_gen_ds512.pdf
...\....\...........\.......\blk_mem_gen_readme.txt
...\....\...........\.......\coregen.cgp
...\....\...........\.......\tmp\_xmsgs\ngcbuild.xmsgs
...\....\...........\.......\...\......\pn_parser.xmsgs
...\....\...........\.......\...\......\xst.xmsgs
...\....\...........\.......\_xmsgs\pn_parser.xmsgs
...\....\...........\FIFO_8bitx2.vhd
...\....\..........4\blk ram\blk_mem_8bitx4\doc\blk_mem_gen_ds512.pdf
...\....\...........\.......\..............\...\blk_mem_gen_v6_1_vinfo.html
...\....\...........\.......\blk_mem_8bitx4.asy
...\....\...........\.......\blk_mem_8bitx4.gise
...\....\...........\.......\blk_mem_8bitx4.ncf
...\....\...........\.......\blk_mem_8bitx4.ngc
...\....\...........\.......\blk_mem_8bitx4.vhd
...\....\...........\.......\blk_mem_8bitx4.vho
...\....\...........\.......\blk_mem_8bitx4.xco
...\....\...........\.......\blk_mem_8bitx4.xise
...\....\...........\.......\blk_mem_8bitx4_flist.txt
...\....\...........\.......\blk_mem_8bitx4_xmdf.tcl
...\....\...........\.......\blk_mem_gen_ds512.pdf
...\....\...........\.......\blk_mem_gen_readme.txt
...\....\...........\.......\coregen.cgp
...\....\...........\.......\tmp\_xmsgs\ngcbuild.xmsgs
...\....\...........\.......\...\......\pn_parser.xmsgs
...\....\...........\.......\...\......\xst.xmsgs
...\....\...........\.......\_xmsgs\pn_parser.xmsgs
...\....\...........\FIFO_8bitx4.vhd
...\RX_IF.vhd
...\TOP_IF.VHD
...\TX_IF.vhd
...\FIFO\FIFO_8bitx2\blk_ram\blk_mem_8bitx2\doc
...\....\...........\.......\tmp\xlnx_auto_0_xdb
...\....\...........\.......\...\_cg
...\....\...........\.......\...\_xmsgs
...\....\..........4\blk ram\blk_mem_8bitx4\doc
...\....\...........\.......\tmp\xlnx_auto_0_xdb
...\....\...........\.......\...\_cg
...\....\...........\.......\...\_xmsgs
...\....\..........2\blk_ram\blk_mem_8bitx2
...\....\...........\.......\tmp
...\....\...........\.......\_xmsgs
...\....\..........4\blk ram\blk_mem_8bitx4
...\....\...........\.......\tmp
...\....\...........\.......\_xmsgs
...\....\..........2\blk_ram
...\....\..........4\blk ram
...\....\FIFO_8bitx2
...\....\FIFO_8bitx4
...\FIFO
RTL

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