Verilog program the FPGA to control the RF chip ADF7021

FPGA_control_ADF7021_v3(add_TDMA_20_10ms)\ADF7021control.bsf
.........................................\ADF7021control.v
.........................................\ADF7021data.bsf
.........................................\ADF7021data.v
.........................................\AMBE_control.bsf
.........................................\AMBE_control.v
.........................................\async_receiver.bsf
.........................................\async_receiver.v
.........................................\async_transmitter.bsf
.........................................\async_transmitter.v
.........................................\FPGA_control_ADF7021.asm.rpt
.........................................\FPGA_control_ADF7021.bdf
.........................................\FPGA_control_ADF7021.done
.........................................\FPGA_control_ADF7021.dpf
.........................................\FPGA_control_ADF7021.fit.rpt
.........................................\FPGA_control_ADF7021.fit.smsg
.........................................\FPGA_control_ADF7021.fit.summary
.........................................\FPGA_control_ADF7021.flow.rpt
.........................................\FPGA_control_ADF7021.jdi
.........................................\FPGA_control_ADF7021.map.rpt
.........................................\FPGA_control_ADF7021.map.smsg
.........................................\FPGA_control_ADF7021.map.summary
.........................................\FPGA_control_ADF7021.pin
.........................................\FPGA_control_ADF7021.pof
.........................................\FPGA_control_ADF7021.qpf
.........................................\FPGA_control_ADF7021.qsf
.........................................\FPGA_control_ADF7021.sof
.........................................\FPGA_control_ADF7021.tan.rpt
.........................................\FPGA_control_ADF7021.tan.summary
.........................................\PLL_ADF7021.bsf
.........................................\PLL_ADF7021.ppf
.........................................\PLL_ADF7021.v
.........................................\PLL_ADF7021_bb.v
.........................................\PLL_ADF7021_wave0.jpg
.........................................\PLL_ADF7021_waveforms.html
.........................................\stp1.stp
.........................................\db
FPGA_control_ADF7021_v3(add_TDMA_20_10ms)

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