FPGA to control the SDRAM project is written in Verilog, easy to use

sdram_mdl\DATAGENE.V
.........\datagene.v.bak
.........\DB\add_sub_4rh.tdf
.........\..\add_sub_6rh.tdf
.........\..\add_sub_918.tdf
.........\..\add_sub_9rh.tdf
.........\..\add_sub_gub.tdf
.........\..\add_sub_ish.tdf
.........\..\add_sub_ksh.tdf
.........\..\add_sub_lsh.tdf
.........\..\add_sub_msh.tdf
.........\..\add_sub_nsh.tdf
.........\..\add_sub_qsh.tdf
.........\..\add_sub_se8.tdf
.........\..\altsyncram_1lh1.tdf
.........\..\altsyncram_5k01.tdf
.........\..\alt_synch_pipe_fv7.tdf
.........\..\alt_synch_pipe_gv7.tdf
.........\..\alt_synch_pipe_oc8.tdf
.........\..\alt_synch_pipe_pc8.tdf
.........\..\alt_sync_fifo_0fm.tdf
.........\..\alt_sync_fifo_0oi.tdf
.........\..\a_fefifo_ctc.tdf
.........\..\a_fefifo_htc.tdf
.........\..\a_gray2bin_meb.tdf
.........\..\a_gray2bin_q4b.tdf
.........\..\a_graycounter_e3c.tdf
.........\..\a_graycounter_f3c.tdf
.........\..\a_graycounter_qa6.tdf
.........\..\a_graycounter_u06.tdf
.........\..\CMPR_746.TDF
.........\..\CNTR_CTA.TDF
.........\..\CNTR_KUA.TDF
.........\..\dcfifo_35l1.tdf
.........\..\dcfifo_cbl1.tdf
.........\..\dcfifo_o2l1.tdf
.........\..\dffpipe_909.tdf
.........\..\dffpipe_a09.tdf
.........\..\dffpipe_c2e.tdf
.........\..\dffpipe_gd9.tdf
.........\..\dffpipe_id9.tdf
.........\..\dffpipe_jd9.tdf
.........\..\dpram_6o31.tdf
.........\..\logic_util_heursitic.dat
.........\..\MUX_1HC.TDF
.........\..\prev_cmp_sdr_test.asm.qmsg
.........\..\prev_cmp_sdr_test.eda.qmsg
.........\..\prev_cmp_sdr_test.fit.qmsg
.........\..\prev_cmp_sdr_test.map.qmsg
.........\..\prev_cmp_sdr_test.qmsg
.........\..\prev_cmp_sdr_test.sim.qmsg
.........\..\prev_cmp_sdr_test.sta.qmsg
.........\..\sdr_test.ae.hdb
.........\..\sdr_test.asm.qmsg
.........\..\sdr_test.asm.rdb
.........\..\sdr_test.cbx.xml
.........\..\sdr_test.cmp.bpm
.........\..\sdr_test.cmp.cbp
.........\..\sdr_test.cmp.cdb
.........\..\sdr_test.cmp.ecobp
.........\..\sdr_test.cmp.hdb
.........\..\sdr_test.cmp.kpt
.........\..\sdr_test.cmp.logdb
.........\..\sdr_test.cmp.rdb
.........\..\sdr_test.cmp0.ddb
.........\..\sdr_test.cmp1.ddb
.........\..\sdr_test.cmp_merge.kpt
.........\..\sdr_test.db_info
.........\..\sdr_test.eco.cdb
.........\..\sdr_test.fit.qmsg
.........\..\sdr_test.hier_info
.........\..\SDR_TEST.HIF
.........\..\sdr_test.lpc.html
.........\..\sdr_test.lpc.rdb
.........\..\sdr_test.lpc.txt
.........\..\sdr_test.map.bpm
.........\..\sdr_test.map.cbp
.........\..\sdr_test.map.cdb
.........\..\sdr_test.map.ecobp
.........\..\sdr_test.map.hdb
.........\..\sdr_test.map.kpt
.........\..\sdr_test.map.logdb
.........\..\sdr_test.map.qmsg
.........\..\sdr_test.map_bb.cdb
.........\..\sdr_test.map_bb.hdb
.........\..\sdr_test.map_bb.logdb
.........\..\sdr_test.pre_map.cdb
.........\..\sdr_test.pre_map.hdb
.........\..\sdr_test.rpp.qmsg
.........\..\sdr_test.rtlv.hdb
.........\..\sdr_test.rtlv_sg.cdb
.........\..\sdr_test.rtlv_sg_swap.cdb
.........\..\sdr_test.sgate.rvd
.........\..\sdr_test.sgate_sm.rvd
.........\..\sdr_test.sgdiff.cdb
.........\..\sdr_test.sgdiff.hdb
.........\..\sdr_test.sim.cvwf
.........\..\sdr_test.sld_design_entry.sci
.........\..\sdr_test.sld_design_entry_dsc.sci
.........\..\sdr_test.smart_action.txt

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