FPGA, using VHDL to create a simple processor (a simple processor)

lab_6\lab_6\ADD_SUB.vhd
.....\.....\ADD_SUB.vhd.bak
.....\.....\control.vhd
.....\.....\control.vhd.bak
.....\.....\counter.vhd
.....\.....\counter.vhd.bak
.....\.....\cpu_1.asm.rpt
.....\.....\cpu_1.done
.....\.....\cpu_1.fit.rpt
.....\.....\cpu_1.fit.smsg
.....\.....\cpu_1.fit.summary
.....\.....\cpu_1.flow.rpt
.....\.....\cpu_1.map.rpt
.....\.....\cpu_1.map.summary
.....\.....\cpu_1.pin
.....\.....\cpu_1.pof
.....\.....\cpu_1.qpf
.....\.....\cpu_1.qsf
.....\.....\cpu_1.qws
.....\.....\cpu_1.sim.rpt
.....\.....\cpu_1.sof
.....\.....\cpu_1.tan.rpt
.....\.....\cpu_1.tan.summary
.....\.....\cpu_1.vhd
.....\.....\cpu_1.vhd.bak
.....\.....\cpu_1.vwf
.....\.....\cpu_1_assignment_defaults.qdf
.....\.....\db\cpu_1.asm.qmsg
.....\.....\..\cpu_1.asm.rdb
.....\.....\..\cpu_1.asm_labs.ddb
.....\.....\..\cpu_1.cbx.xml
.....\.....\..\cpu_1.cmp.bpm
.....\.....\..\cpu_1.cmp.cdb
.....\.....\..\cpu_1.cmp.ecobp
.....\.....\..\cpu_1.cmp.hdb
.....\.....\..\cpu_1.cmp.kpt
.....\.....\..\cpu_1.cmp.logdb
.....\.....\..\cpu_1.cmp.rdb
.....\.....\..\cpu_1.cmp.tdb
.....\.....\..\cpu_1.cmp0.ddb
.....\.....\..\cpu_1.cmp_merge.kpt
.....\.....\..\cpu_1.db_info
.....\.....\..\cpu_1.eco.cdb
.....\.....\..\cpu_1.eds_overflow
.....\.....\..\cpu_1.fit.qmsg
.....\.....\..\cpu_1.fnsim.cdb
.....\.....\..\cpu_1.fnsim.hdb
.....\.....\..\cpu_1.fnsim.qmsg
.....\.....\..\cpu_1.hier_info
.....\.....\..\cpu_1.hif
.....\.....\..\cpu_1.lpc.html
.....\.....\..\cpu_1.lpc.rdb
.....\.....\..\cpu_1.lpc.txt
.....\.....\..\cpu_1.map.bpm
.....\.....\..\cpu_1.map.cdb
.....\.....\..\cpu_1.map.ecobp
.....\.....\..\cpu_1.map.hdb
.....\.....\..\cpu_1.map.kpt
.....\.....\..\cpu_1.map.logdb
.....\.....\..\cpu_1.map.qmsg
.....\.....\..\cpu_1.map_bb.cdb
.....\.....\..\cpu_1.map_bb.hdb
.....\.....\..\cpu_1.map_bb.logdb
.....\.....\..\cpu_1.pre_map.cdb
.....\.....\..\cpu_1.pre_map.hdb
.....\.....\..\cpu_1.rtlv.hdb
.....\.....\..\cpu_1.rtlv_sg.cdb
.....\.....\..\cpu_1.rtlv_sg_swap.cdb
.....\.....\..\cpu_1.sgdiff.cdb
.....\.....\..\cpu_1.sgdiff.hdb
.....\.....\..\cpu_1.sim.cvwf
.....\.....\..\cpu_1.sim.hdb
.....\.....\..\cpu_1.sim.qmsg
.....\.....\..\cpu_1.sim.rdb
.....\.....\..\cpu_1.simfam
.....\.....\..\cpu_1.sld_design_entry.sci
.....\.....\..\cpu_1.sld_design_entry_dsc.sci
.....\.....\..\cpu_1.smart_action.txt
.....\.....\..\cpu_1.syn_hier_info
.....\.....\..\cpu_1.tan.qmsg
.....\.....\..\cpu_1.tis_db_list.ddb
.....\.....\..\logic_util_heursitic.dat
.....\.....\..\mux_5oc.tdf
.....\.....\..\mux_kpc.tdf
.....\.....\..\mux_lpc.tdf
.....\.....\..\prev_cmp_cpu_1.asm.qmsg
.....\.....\..\prev_cmp_cpu_1.fit.qmsg
.....\.....\..\prev_cmp_cpu_1.map.qmsg
.....\.....\..\prev_cmp_cpu_1.qmsg
.....\.....\..\prev_cmp_cpu_1.sim.qmsg
.....\.....\..\prev_cmp_cpu_1.tan.qmsg
.....\.....\..\wed.wsf
.....\.....\incremental_db\compiled_partitions\cpu_1.root_partition.cmp.atm
.....\.....\..............\...................\cpu_1.root_partition.cmp.cdb
.....\.....\..............\...................\cpu_1.root_partition.cmp.cfm
.....\.....\..............\...................\cpu_1.root_partition.cmp.dfp
.....\.....\..............\...................\cpu_1.root_partition.cmp.hdb
.....\.....\..............\...................\cpu_1.root_partition.cmp.hdbx
.....\.....\..............\...................\cpu_1.root_partition.cmp.kpt
.....\.....\..............\...................\cpu_1.root_partition.cmp.logdb

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