“Randomized Smoothing Networks” introduced the idea of using networks composed of a type of comparator/memory element, initialized to random initial states, to create smoothing networks, which take arbitrary input loads into the network and produce an output that balances the load among all the outputs in a predictable manner. I created a synthesizable Verilog model of these comparator/memory elements (or “balancers”), and used a pseudo-random linear feedback shift register (LFSR) to toggle all possible initial random states for two of the proposed RSNs configurations, the Block network and the Butterfly network, verifying the results of Herlihy and Tirthapura.

balancer.v
balancerAsynch.v
block8Asynch.v
blockAsynch.files
blockRun
butterfly.files
butterfly16.v
butterfly16Asynch.v
butterfly32Asynch.v
butterfly8.v
butterfly8Asynch.v
butterflyAsynch.files
butterflyRun
cds.lib
cshark
LFSR2_32.v
Randomized Smoothing Networks 2.ppt
README
RSN.doc
rsv.v
runButterfly
runButterflyAsynch
runLFSR
runScript
xilinxCompile
tb_8wire.v
tb_8wire_block.v
tb_8wire_butterfly.orig.v
tb_8wire_butterfly.v
tb_balancer.v
tb_balancerAsynch.v
tb_butterfly16Asynch.v
tb_butterfly8.v
tb_butterfly8Asynch.v
tb_butterfly8Asynch2.v
hdl.var

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