Verilog basic useful for verilog beginners.

verilog_lecture\lab\lab1\add16.v
...............\...\lab1
...............\...\....0\test_pli.v
...............\...\.....\veriuser.c
...............\...\lab10
...............\...\...4\clk_chain.sdf
...............\...\....\clk_chain.v
...............\...\lab4
...............\...\...5\case.v
...............\...\....\design.sdf
...............\...\....\design.v
...............\...\....\ifthen.v
...............\...\....\multi_bit_access.v
...............\...\....\single_word_access.v
...............\...\lab5
...............\...\...9\violation.v
...............\...\lab9
...............\lab
...............\..._solution\lab1\add16.v
...............\............\lab1
...............\............\...2\add16.v
...............\............\....\mulitplier.v
...............\............\....\mulitplier_add.v
...............\............\....\top.v
...............\............\lab2
...............\............\...3\lab3.v
...............\............\lab3
...............\............\...4\clk_chain.sdf
...............\............\....\clk_chain.v
...............\............\lab4
...............\............\...5\case.v
...............\............\....\design.sdf
...............\............\....\design.v
...............\............\....\ifthen.v
...............\............\....\multi_bit_access.v
...............\............\....\single_word_access.v
...............\............\lab5
...............\............\...6\add16.v
...............\............\....\mulitplier_add.v
...............\............\....\top.v
...............\............\lab6
...............\............\...7\binary\state.v
...............\............\....\......\top.v
...............\............\....\binary
...............\............\....\one-hot\state_onehot.v
...............\............\....\.......\top_onehot.v
...............\............\....\one-hot
...............\............\lab7
...............\............\...8\initial.v
...............\............\lab8
...............\............\...9\mux2.v
...............\............\....\violation.v
...............\............\lab9
...............\lab_solution
...............\verilog_lecture.ppt
verilog_lecture

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