FPGA and gate source code, and function: the two input signals phase and results output! Using the Verilog HDL language programming

ander\ander.ise_ISE_Backup
.....\ande.v
.....\__projnav.log
.....\automake.log
.....\logic.ucf
.....\__projnav\sumrpt_tcl.rsp
.....\.........\runXst_tcl.rsp
.....\.........\logic_edfTOngd_tcl.rsp
.....\.........\ander_flowplus.gfl
.....\.........\ander.gfl
.....\.........\logic.xst
.....\.........\parentAssignPackagePinsApp_tcl.rsp
.....\.........\parentEditConstraintsTextApp_tcl.rsp
.....\.........\ande_edfTOngd_tcl.rsp
.....\.........\ande.xst
.....\.........\jhdparse.log
.....\logic.prj
.....\logic.cmd_log
.....\logic.syr
.....\logic.lso
.....\logic_vhdl.prj
.....\ande.ucf
.....\ande.prj
.....\ande.cmd_log
.....\ande.syr
.....\ande.lso
.....\ande.lfp
.....\_pace.ucf
.....\ande.spl
.....\ande.sym
.....\ande_vhdl.prj
.....\xst\work\vlg74\ande.bin
.....\...\....\hdllib.ref
.....\ande.ngr
.....\ande.ngc
.....\ande.stx
.....\...._html\fit\applet.js
.....\.........\...\appletref.htm
.....\.........\...\asciidoc.htm
.....\.........\...\backtop.jpg
.....\.........\...\beginstraight.gif
.....\.........\...\blank.gif
.....\.........\...\blank.htm
.....\.........\...\briefview.jpg
.....\.........\...\check.htm
.....\.........\...\checkNS4.htm
.....\.........\...\contact.gif
.....\.........\...\coolrunnerII_logo.jpg
.....\.........\...\coolrunner_logo.jpg
.....\.........\...\education.gif
.....\.........\...\endmkt.gif
.....\.........\...\eqns.js
.....\.........\...\equations.gif
.....\.........\...\equations.htm
.....\.........\...\equationsdoc.htm
.....\.........\...\errors.js
.....\.........\...\errors1.gif
.....\.........\...\errors2.gif
.....\.........\...\errorsdoc.htm
.....\.........\...\failtable.js
.....\.........\...\failtabledoc.htm
.....\.........\...\fb.gif
.....\.........\...\fb1.gif
.....\.........\...\fbs.js
.....\.........\...\fbs_FBdoc.htm
.....\.........\...\fbsdoc.htm
.....\.........\...\fbview.jpg
.....\.........\...\functionblock.gif
.....\.........\...\genmsg.htm
.....\.........\...\header.gif
.....\.........\...\home.gif
.....\.........\...\index.htm
.....\.........\...\inputleft.js
.....\.........\...\inputleftdoc.htm
.....\.........\...\leftnav.js
.....\.........\...\legend.gif
.....\.........\...\legend.jpg
.....\.........\...\logic_legXC95.htm
.....\.........\...\logic_legXbr.htm
.....\.........\...\logic_legXpla3.htm
.....\.........\...\logicleft.js
.....\.........\...\logicleftdoc.htm
.....\.........\...\macrocell.gif
.....\.........\...\mapinputdoc.htm
.....\.........\...\maplogic.js
.....\.........\...\maplogicdoc.htm
.....\.........\...\newappletref.htm
.....\.........\...\next.jpg
.....\.........\...\ns4plugin.js
.....\.........\...\optionsdoc.htm
.....\.........\...\paths.js
.....\.........\...\pin.gif
.....\.........\...\pin_legXC95.htm
.....\.........\...\pin_legXbr.htm
.....\.........\...\pin_legXpla3.htm
.....\.........\...\pindiagram.gif
.....\.........\...\pins.js
.....\.........\...\pinsdoc.htm
.....\.........\...\pinview.jpg
.....\.........\...\plugin.js

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．