FPGA implementation of DPLL, the use of hardware description council meeting Verilog HDL top-level file DPLL is. V

FdplllzipP\dpll\divfrequency32.v
..........\....\divfrequency32_tp.v
..........\....\divfrequency64.v
..........\....\divfrequency64_tp.v
..........\....\divfrequency8.v
..........\....\divfrequency8_tp.v
..........\....\dpll.v
..........\....\dpll_tp.v
..........\....\maichongjiajian.v
..........\....\maichongjiajian_tp.v
..........\....\moKcounter.v
..........\....\moKcounter_tp.v
..........\....\xorphd.v
..........\....\xorphd_tp.v
..........\dpll
FdplllzipP

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