CPU design

lab06_吴纯纯_王景峰_王少萍_谢志宇
.................................\PipelineCPU
.................................\...........\ALU.v
.................................\...........\ALU.v.bak
.................................\...........\BarrelShifter.v
.................................\...........\BarrelShifter.v.bak
.................................\...........\ControlHazard.v
.................................\...........\ControlHazard.v.bak
.................................\...........\ControlUnit.v
.................................\...........\ControlUnit.v.bak
.................................\...........\DataMemory.v
.................................\...........\DataMemory.v.bak
.................................\...........\Ex_Mem.v
.................................\...........\Ex_Mem.v.bak
.................................\...........\Extender.v
.................................\...........\ForwardUnit.v
.................................\...........\ForwardUnit.v.bak
.................................\...........\ID_Ex.v
.................................\...........\ID_Ex.v.bak
.................................\...........\IF_ID.v
.................................\...........\IF_ID.v.bak
.................................\...........\InstMemory.v
.................................\...........\InstMemory.v.bak
.................................\...........\LoadUseDetector.v
.................................\...........\LoadUseDetector.v.bak
.................................\...........\LoadWordUnit.v
.................................\...........\LoadWordUnit.v.bak
.................................\...........\Mem_Wr.v
.................................\...........\Mem_Wr.v.bak
.................................\...........\Mux3_1.v
.................................\...........\Mux3_1.v.bak
.................................\...........\Mux4_1.v
.................................\...........\Mux4_1.v.bak
.................................\...........\Mux_32.v
.................................\...........\Mux_5.v
.................................\...........\PCSourceGenerator.v
.................................\...........\PCSourceGenerator.v.bak
.................................\...........\PCount.v
.................................\...........\PCount.v.bak
.................................\...........\PipelineCPU.qpf
.................................\...........\PipelineCPU.qsf
.................................\...........\PipelineCPU.v
.................................\...........\PipelineCPU.v.bak
.................................\...........\PipelineCPU.vwf
.................................\...........\PipelineCPU_assignment_defaults.qdf
.................................\...........\RegisterGroup.v
.................................\...........\RegisterGroup.v.bak
.................................\...........\db
.................................\...........\..\PipelineCPU.db_info
.................................\...........\..\PipelineCPU.eco.cdb
.................................\...........\..\PipelineCPU.sim.cvwf
.................................\...........\..\PipelineCPU.sld_design_entry.sci
.................................\...........\..\altsyncram_02j1.tdf
.................................\...........\..\altsyncram_4nq1.tdf
.................................\...........\..\altsyncram_bb01.tdf
.................................\...........\..\altsyncram_mjj1.tdf
.................................\...........\..\altsyncram_mnv.tdf
.................................\...........\..\altsyncram_ohn1.tdf
.................................\...........\..\altsyncram_sqv.tdf
.................................\...........\..\mux_3nc.tdf
.................................\...........\..\mux_aqc.tdf
.................................\...........\..\mux_d3d.tdf
.................................\...........\..\mux_ioc.tdf
.................................\...........\..\mux_umc.tdf
.................................\...........\..\prev_cmp_PipelineCPU.map.qmsg
.................................\...........\..\prev_cmp_PipelineCPU.qmsg
.......

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