CPU design

lab05_091220116吴纯纯
.....................\visio
.....................\.....\多周期CPU数据通路.vsd
.....................\.....\指令执行状态转换图.vsd
.....................\~$实验报告.docx
.....................\代码
.....................\....\ALU.v
.....................\....\CPU_control.v
.....................\....\I_type_control.v
.....................\....\R_type_control.v
.....................\....\extender.v
.....................\....\memory.v
.....................\....\multi_cpu.v
.....................\....\register_single.v
.....................\....\registers.v
.....................\....\selector1.v
.....................\....\selector32.v
.....................\....\selector32_3.v
.....................\....\selector32_4.v
.....................\....\selector32_L.v
.....................\....\selector4_3.v
.....................\....\selector5.v
.....................\....\shift.v
.....................\多周期CPU
.....................\.........\ALU.v
.....................\.........\CPU_control.v
.....................\.........\CPU_control.v.bak
.....................\.........\I_type_control.v
.....................\.........\I_type_control.v.bak
.....................\.........\R_type_control.v
.....................\.........\R_type_control.v.bak
.....................\.........\db
.....................\.........\..\multi_cpu.cbx.xml
.....................\.........\..\multi_cpu.db_info
.....................\.........\..\multi_cpu.eco.cdb
.....................\.........\..\multi_cpu.eds_overflow
.....................\.........\..\multi_cpu.fnsim.cdb
.....................\.........\..\multi_cpu.fnsim.hdb
.....................\.........\..\multi_cpu.fnsim.qmsg
.....................\.........\..\multi_cpu.hier_info
.....................\.........\..\multi_cpu.lpc.html
.....................\.........\..\multi_cpu.lpc.rdb
.....................\.........\..\multi_cpu.lpc.txt
.....................\.........\..\multi_cpu.sim.cvwf
.....................\.........\..\multi_cpu.sim.hdb
.....................\.........\..\multi_cpu.sim.qmsg
.....................\.........\..\multi_cpu.sim.rdb
.....................\.........\..\multi_cpu.simfam
.....................\.........\..\multi_cpu.sld_design_entry.sci
.....................\.........\..\multi_cpu.sld_design_entry_dsc.sci
.....................\.........\..\multi_cpu.smart_action.txt
.....................\.........\..\mux_3nc.tdf
.....................\.........\..\mux_aqc.tdf
.....................\.........\..\mux_ioc.tdf
.....................\.........\..\mux_joc.tdf
.....................\.........\..\prev_cmp_multi_cpu.map.qmsg
.....................\.........\..\prev_cmp_multi_cpu.qmsg
.....................\.........\..\prev_cmp_multi_cpu.sim.qmsg
.....................\.........\..\wed.wsf
.....................\.........\debug
.....................\.........\.....\multi_cpu.done
.....................\.........\.....\multi_cpu.flow.rpt
.....................\.........\.....\multi_cpu.map.rpt
.....................\.........\.....\multi_cpu.map.smsg
.....................\.........\.....\multi_cpu.map.summary
.....................\.........\.....\multi_cpu.sim.rpt
.....................\.........\extender.v
.....................\.........\incremental_db
.....................\.........\..............\README
.....................\.........\..............\compiled_partitions
.....................\.........\..............\...................\multi_cpu.root_partition.map.atm
.....................\.........\..............\...................\multi_cpu.root_partition.map.cdb
.....................\.........\..............\...................\multi_cpu.root_partition.map.dpi
.....................\.........\..............\...................\multi_cpu.root_partition.map.hdb
.....................\.........\..............\...................\multi_cpu.root_partition.map.hdbx
.....................\.........\..............\...................\multi_cpu.root_partition.map.kpt
.....................\.........\memory.v
.....................\.........\memory.v.bak
.....................\.........\multi_cpu.q

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