LDR This a project.

LDR

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Category : VHDL-FPGA-Verilog
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Update : 2012-11-26
Size : 21kb
Downloaded ：0次
Author ：Biswaji*******
About ： Nobody
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Introduction - If you have any usage issues, please Google them yourself

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This a LDR project.

Packet file list

(Preview for download)

LDR_Con.opj
LDR_CON.DBK
LDR_CON.DSN
LDR_CON-SCHEMATIC1.ALS
ldr_con-SCHEMATIC1-biaspoint.out
ldr_con-SCHEMATIC1-biaspoint.sim
ldr_con-SCHEMATIC1-biaspoint.mrk
ldr_con-SCHEMATIC1-biaspoint.sim.cir
ldr_con-SCHEMATIC1-biaspoint.sim.1OP
ldr_con-SCHEMATIC1-Parametric.out
ldr_con-SCHEMATIC1-Parametric.sim
ldr_con-SCHEMATIC1-Parametric.mrk
ldr_con-SCHEMATIC1-Parametric.sim.cir
ldr_con-SCHEMATIC1-Parametric.sim.1OP
Dn Counter.opj
DN COUNTER.DSN
dn counter-SCHEMATIC1-Default.mrk

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