FPGA classic frequency plan, use the complete VHDL language, have enough comments, a look at wi

plj_a\my_library\al_logic.bsf
.....\..........\cnt10a.bsf
.....\..........\cnt10b.bsf
.....\..........\cnt10c.bsf
.....\..........\cnt6a.bsf
.....\..........\ctrl_a.bsf
.....\..........\decode_disp.bsf
.....\..........\divf1hz.bsf
.....\..........\divf50m_1hz.bsf
.....\..........\latch0a.bsf
.....\..........\plj_a.bsf
.....\..........\sm_disp.bsf
.....\..........\sm_flash.bsf
.....\quartus\control_a.vwf
.....\.......\db\plj_a.asm.qmsg
.....\.......\..\plj_a.asm_labs.ddb
.....\.......\..\plj_a.atom.rvd
.....\.......\..\plj_a.atom_map.rvd
.....\.......\..\plj_a.cbx.xml
.....\.......\..\plj_a.cmp.bpm
.....\.......\..\plj_a.cmp.cdb
.....\.......\..\plj_a.cmp.ecobp
.....\.......\..\plj_a.cmp.hdb
.....\.......\..\plj_a.cmp.kpt
.....\.......\..\plj_a.cmp.logdb
.....\.......\..\plj_a.cmp.rdb
.....\.......\..\plj_a.cmp.tdb
.....\.......\..\plj_a.cmp0.ddb
.....\.......\..\plj_a.cmp2.ddb
.....\.......\..\plj_a.cmp_merge.kpt
.....\.......\..\plj_a.db_info
.....\.......\..\plj_a.eco.cdb
.....\.......\..\plj_a.eds_overflow
.....\.......\..\plj_a.fit.qmsg
.....\.......\..\plj_a.fnsim.hdb
.....\.......\..\plj_a.fnsim.qmsg
.....\.......\..\plj_a.hier_info
.....\.......\..\plj_a.hif
.....\.......\..\plj_a.lpc.html
.....\.......\..\plj_a.lpc.rdb
.....\.......\..\plj_a.lpc.txt
.....\.......\..\plj_a.map.bpm
.....\.......\..\plj_a.map.cdb
.....\.......\..\plj_a.map.ecobp
.....\.......\..\plj_a.map.hdb
.....\.......\..\plj_a.map.kpt
.....\.......\..\plj_a.map.logdb
.....\.......\..\plj_a.map.qmsg
.....\.......\..\plj_a.map_bb.cdb
.....\.......\..\plj_a.map_bb.hdb
.....\.......\..\plj_a.map_bb.logdb
.....\.......\..\plj_a.pre_map.cdb
.....\.......\..\plj_a.pre_map.hdb
.....\.......\..\plj_a.rpp.qmsg
.....\.......\..\plj_a.rtlv.hdb
.....\.......\..\plj_a.rtlv_sg.cdb
.....\.......\..\plj_a.rtlv_sg_swap.cdb
.....\.......\..\plj_a.sgate_sm.rvd
.....\.......\..\plj_a.sgdiff.cdb
.....\.......\..\plj_a.sgdiff.hdb
.....\.......\..\plj_a.sim.cvwf
.....\.......\..\plj_a.sim.hdb
.....\.......\..\plj_a.sim.qmsg
.....\.......\..\plj_a.sim.rdb
.....\.......\..\plj_a.simfam
.....\.......\..\plj_a.sld_design_entry.sci
.....\.......\..\plj_a.sld_design_entry_dsc.sci
.....\.......\..\plj_a.syn_hier_info
.....\.......\..\plj_a.tan.qmsg
.....\.......\..\plj_a.tis_db_list.ddb
.....\.......\..\plj_a.tmw_info
.....\.......\..\prev_cmp_plj_a.asm.qmsg
.....\.......\..\prev_cmp_plj_a.fit.qmsg
.....\.......\..\prev_cmp_plj_a.map.qmsg
.....\.......\..\prev_cmp_plj_a.qmsg
.....\.......\..\prev_cmp_plj_a.tan.qmsg
.....\.......\..\wed.wsf
.....\.......\fpgac8.tcl
.....\.......\fpgac8.tcl.bak
.....\.......\incremental_db\compiled_partitions\plj_a.root_partition.cmp.atm
.....\.......\..............\...................\plj_a.root_partition.cmp.dfp
.....\.......\..............\...................\plj_a.root_partition.cmp.hdbx
.....\.......\..............\...................\plj_a.root_partition.cmp.kpt
.....\.......\..............\...................\plj_a.root_partition.cmp.logdb
.....\.......\..............\...................\plj_a.root_partition.cmp.rcf
.....\.......\..............\...................\plj_a.root_partition.map.atm
.....\.......\..............\...................\plj_a.root_partition.map.dpi
.....\.......\..............\...................\plj_a.root_partition.map.hdbx
.....\.......\..............\...................\plj_a.root_partition.map.kpt
.....\.......\..............\README
.....\.......\mytest.tcl
.....\.......\mytest.tcl.bak
.....\.......\plj_a.asm.rpt
.....\.......\plj_a.done
.....\.......\plj_a.dpf
.....\.......\plj_a.fit.rpt
.....\.......\plj_a.fit.smsg
.....\.......\plj_a.fit.summary
.....\.......\plj_a.flow.rpt
.....\.......\plj_a.map.rpt

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