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DE2_115_golden_sopc_new

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 40.09mb
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  • Author :xut***
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Introduction - If you have any usage issues, please Google them yourself
nios II triple-core processors share a memory sharing of resources. Using the DE2-115 development board. (Mutex)
Packet file list
(Preview for download)
DE2_115_golden_sopc_new
.......................\.qsys_edit
.......................\..........\filters.xml
.......................\..........\preferences.xml
.......................\.sopc_builder
.......................\.............\filters.xml
.......................\.............\install.ptf
.......................\.............\install2.ptf
.......................\.............\preferences.xml
.......................\altpll.v
.......................\altpllpll.qip
.......................\altpllpll.v
.......................\altpllpll_0.qip
.......................\altpllpll_0.v
.......................\altpllpll_0_bb.v
.......................\altpllpll_bb.v
.......................\audio.v
.......................\clock_crossing_io.v
.......................\cpu.ocp
.......................\cpu.sdc
.......................\cpu.v
.......................\cpu0.ocp
.......................\cpu0.sdc
.......................\cpu0.v
.......................\cpu0_bht_ram.mif
.......................\cpu0_dc_tag_ram.mif
.......................\cpu0_ic_tag_ram.mif
.......................\cpu0_jtag_debug_module_sysclk.v
.......................\cpu0_jtag_debug_module_tck.v
.......................\cpu0_jtag_debug_module_wrapper.v
.......................\cpu0_memory.hex
.......................\cpu0_memory.v
.......................\cpu0_mult_cell.v
.......................\cpu0_ociram_default_contents.mif
.......................\cpu0_oci_test_bench.v
.......................\cpu0_rf_ram_a.mif
.......................\cpu0_rf_ram_b.mif
.......................\cpu0_test_bench.v
.......................\cpu1.ocp
.......................\cpu1.sdc
.......................\cpu1.v
.......................\cpu1timer.v
.......................\cpu1_bht_ram.mif
.......................\cpu1_dc_tag_ram.mif
.......................\cpu1_ic_tag_ram.mif
.......................\cpu1_jtag_debug_module_sysclk.v
.......................\cpu1_jtag_debug_module_tck.v
.......................\cpu1_jtag_debug_module_wrapper.v
.......................\cpu1_memory.hex
.......................\cpu1_memory.v
.......................\cpu1_mult_cell.v
.......................\cpu1_ociram_default_contents.mif
.......................\cpu1_oci_test_bench.v
.......................\cpu1_rf_ram_a.mif
.......................\cpu1_rf_ram_b.mif
.......................\cpu1_test_bench.v
.......................\cpu2.ocp
.......................\cpu2.sdc
.......................\cpu2.v
.......................\cpu2timer.v
.......................\cpu2_bht_ram.mif
.......................\cpu2_dc_tag_ram.mif
.......................\cpu2_ic_tag_ram.mif
.......................\cpu2_jtag_debug_module_sysclk.v
.......................\cpu2_jtag_debug_module_tck.v
.......................\cpu2_jtag_debug_module_wrapper.v
.......................\cpu2_mult_cell.v
.......................\cpu2_ociram_default_contents.mif
.......................\cpu2_oci_test_bench.v
.......................\cpu2_rf_ram_a.mif
.......................\cpu2_rf_ram_b.mif
.......................\cpu2_test_bench.v
.......................\cpu_1.ocp
.......................\cpu_1.sdc
.......................\cpu_1.v
.......................\cpu_1_ic_tag_ram.mif
.......................\cpu_1_jtag_debug_module_sysclk.v
.......................\cpu_1_jtag_debug_module_tck.v
.......................\cpu_1_jtag_debug_module_wrapper.v
.......................\cpu_1_mult_cell.v
.......................\cpu_1_ociram_default_contents.mif
.......................\cpu_1_oci_test_bench.v
.......................\cpu_1_rf_ram_a.mif
.......................\cpu_1_rf_ram_b.mif
.......................\cpu_1_test_bench.v
.......................\cpu_2.ocp
.......................\cpu_2.sdc
.......................\cpu_2.v
.......................\cpu_2_ic_tag_ram.mif
.......................\cpu_2_jtag_debug_module_sysclk.v
.......................\cpu_2_jtag_debug_module_tck.v
.......................\cpu_2_jtag_debug_module_wrapper.v
.......................\cpu_2_mult_cell.v
.......................\cpu_2_ociram_default_contents.mif
.......................\cpu_2_oci_test_benc
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