QPSK modulation and demodulation of the FPGA, including the pseudo-code generation modules

chenyu_fpga\chenyu_fpga.asm.rpt
...........\chenyu_fpga.done
...........\chenyu_fpga.eda.rpt
...........\chenyu_fpga.fit.rpt
...........\chenyu_fpga.fit.smsg
...........\chenyu_fpga.fit.summary
...........\chenyu_fpga.flow.rpt
...........\chenyu_fpga.map.rpt
...........\chenyu_fpga.map.summary
...........\chenyu_fpga.pin
...........\chenyu_fpga.pof
...........\chenyu_fpga.qpf
...........\chenyu_fpga.qsf
...........\chenyu_fpga.sof
...........\chenyu_fpga.tan.rpt
...........\chenyu_fpga.v
...........\chenyu_fpga.v.bak
...........\chenyu_fpga_nativelink_simulation.rpt
...........\counter_9.v
...........\counter_9.v.bak
...........\db\chenyu_fpga.asm.qmsg
...........\..\chenyu_fpga.asm.rdb
...........\..\chenyu_fpga.asm_labs.ddb
...........\..\chenyu_fpga.cbx.xml
...........\..\chenyu_fpga.cmp.bpm
...........\..\chenyu_fpga.cmp.cdb
...........\..\chenyu_fpga.cmp.ecobp
...........\..\chenyu_fpga.cmp.hdb
...........\..\chenyu_fpga.cmp.kpt
...........\..\chenyu_fpga.cmp.logdb
...........\..\chenyu_fpga.cmp.rdb
...........\..\chenyu_fpga.cmp.tdb
...........\..\chenyu_fpga.cmp0.ddb
...........\..\chenyu_fpga.cmp_merge.kpt
...........\..\chenyu_fpga.db_info
...........\..\chenyu_fpga.eco.cdb
...........\..\chenyu_fpga.eda.qmsg
...........\..\chenyu_fpga.fit.qmsg
...........\..\chenyu_fpga.hier_info
...........\..\chenyu_fpga.hif
...........\..\chenyu_fpga.lpc.html
...........\..\chenyu_fpga.lpc.rdb
...........\..\chenyu_fpga.lpc.txt
...........\..\chenyu_fpga.map.bpm
...........\..\chenyu_fpga.map.cdb
...........\..\chenyu_fpga.map.ecobp
...........\..\chenyu_fpga.map.hdb
...........\..\chenyu_fpga.map.kpt
...........\..\chenyu_fpga.map.logdb
...........\..\chenyu_fpga.map.qmsg
...........\..\chenyu_fpga.map_bb.cdb
...........\..\chenyu_fpga.map_bb.hdb
...........\..\chenyu_fpga.map_bb.logdb
...........\..\chenyu_fpga.pre_map.cdb
...........\..\chenyu_fpga.pre_map.hdb
...........\..\chenyu_fpga.rtlv.hdb
...........\..\chenyu_fpga.rtlv_sg.cdb
...........\..\chenyu_fpga.rtlv_sg_swap.cdb
...........\..\chenyu_fpga.sgdiff.cdb
...........\..\chenyu_fpga.sgdiff.hdb
...........\..\chenyu_fpga.sld_design_entry.sci
...........\..\chenyu_fpga.sld_design_entry_dsc.sci
...........\..\chenyu_fpga.smart_action.txt
...........\..\chenyu_fpga.syn_hier_info
...........\..\chenyu_fpga.tan.qmsg
...........\..\chenyu_fpga.tis_db_list.ddb
...........\..\logic_util_heursitic.dat
...........\..\prev_cmp_chenyu_fpga.asm.qmsg
...........\..\prev_cmp_chenyu_fpga.eda.qmsg
...........\..\prev_cmp_chenyu_fpga.fit.qmsg
...........\..\prev_cmp_chenyu_fpga.map.qmsg
...........\..\prev_cmp_chenyu_fpga.qmsg
...........\..\prev_cmp_chenyu_fpga.tan.qmsg
...........\div_15.v
...........\div_15.v.bak
...........\incremental_db\compiled_partitions\chenyu_fpga.root_partition.cmp.cdb
...........\..............\...................\chenyu_fpga.root_partition.cmp.dfp
...........\..............\...................\chenyu_fpga.root_partition.cmp.hdb
...........\..............\...................\chenyu_fpga.root_partition.cmp.kpt
...........\..............\...................\chenyu_fpga.root_partition.cmp.logdb
...........\..............\...................\chenyu_fpga.root_partition.cmp.rcfdb
...........\..............\...................\chenyu_fpga.root_partition.cmp.re.rcfdb
...........\..............\...................\chenyu_fpga.root_partition.map.cdb
...........\..............\...................\chenyu_fpga.root_partition.map.dpi
...........\..............\...................\chenyu_fpga.root_partition.map.hdb
...........\..............\...................\chenyu_fpga.root_partition.map.kpt
...........\..............\README
...........\pr_code_gen.v
...........\pr_code_gen.v.bak
...........\QPSK_C.v
...........\QPSK_C.v.bak
...........\QPSK_IQ_demodulate.v
...........\QPSK_IQ_demodulate.v.bak
...........\qpsk_iq_modulate.v
...........\qpsk_iq_modulate.v.bak
...........\simulation\modelsim\chenyu_fpga.sft
...........\..........\........\chenyu_fpga.vo
...........\..........\........\chenyu_fpga.vt
...........\..........\........\chenyu_fpga.vt.bak
...........\.....

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