This contains VHDL source code for a simple arithmetic logic unit. the input and results are displayed on a 4 digit 7 segment display. The user controls the input throug the use of switches. This design was created for the nexys 2 fpga but can be easily ported to other fpga s.

clock_divider.txt
four_bit_alu.txt
input_decoder.txt
multiplexer.txt
Nexys2_500General.ucf
number_decoder.txt
pin_config.ucf
text_decoder.txt
top_level.txt

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