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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 2.2mb
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  • Author :林****
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Introduction - If you have any usage issues, please Google them yourself
16550uart very complete utility which contains all the files
Packet file list
(Preview for download)
16550\db\altsyncram_vud1.tdf
.....\..\prev_cmp_uart_top.asm.qmsg
.....\..\prev_cmp_uart_top.eda.qmsg
.....\..\prev_cmp_uart_top.fit.qmsg
.....\..\prev_cmp_uart_top.map.qmsg
.....\..\prev_cmp_uart_top.tan.qmsg
.....\..\uart.smp_dump.txt
.....\..\uart_top.asm.qmsg
.....\..\uart_top.cbx.xml
.....\..\uart_top.cmp.bpm
.....\..\uart_top.cmp.cdb
.....\..\uart_top.cmp.ecobp
.....\..\uart_top.cmp.hdb
.....\..\uart_top.cmp.kpt
.....\..\uart_top.cmp.logdb
.....\..\uart_top.cmp.rdb
.....\..\uart_top.cmp.tdb
.....\..\uart_top.cmp0.ddb
.....\..\uart_top.cmp_merge.kpt
.....\..\uart_top.db_info
.....\..\uart_top.eco.cdb
.....\..\uart_top.eda.qmsg
.....\..\uart_top.fit.qmsg
.....\..\uart_top.hier_info
.....\..\uart_top.hif
.....\..\uart_top.lpc.html
.....\..\uart_top.lpc.rdb
.....\..\uart_top.lpc.txt
.....\..\uart_top.map.bpm
.....\..\uart_top.map.cdb
.....\..\uart_top.map.ecobp
.....\..\uart_top.map.hdb
.....\..\uart_top.map.kpt
.....\..\uart_top.map.logdb
.....\..\uart_top.map.qmsg
.....\..\uart_top.map_bb.cdb
.....\..\uart_top.map_bb.hdb
.....\..\uart_top.map_bb.logdb
.....\..\uart_top.pre_map.cdb
.....\..\uart_top.pre_map.hdb
.....\..\uart_top.rpp.qmsg
.....\..\uart_top.rtlv.hdb
.....\..\uart_top.rtlv_sg.cdb
.....\..\uart_top.rtlv_sg_swap.cdb
.....\..\uart_top.sgate.rvd
.....\..\uart_top.sgate_sm.rvd
.....\..\uart_top.sgdiff.cdb
.....\..\uart_top.sgdiff.hdb
.....\..\uart_top.sld_design_entry.sci
.....\..\uart_top.sld_design_entry_dsc.sci
.....\..\uart_top.syn_hier_info
.....\..\uart_top.tan.qmsg
.....\..\uart_top.tis_db_list.ddb
.....\..\uart_top.tmw_info
.....\incremental_db\compiled_partitions\uart_top.root_partition.cmp.atm
.....\..............\...................\uart_top.root_partition.cmp.dfp
.....\..............\...................\uart_top.root_partition.cmp.hdbx
.....\..............\...................\uart_top.root_partition.cmp.kpt
.....\..............\...................\uart_top.root_partition.cmp.logdb
.....\..............\...................\uart_top.root_partition.cmp.rcf
.....\..............\...................\uart_top.root_partition.map.atm
.....\..............\...................\uart_top.root_partition.map.dpi
.....\..............\...................\uart_top.root_partition.map.hdbx
.....\..............\...................\uart_top.root_partition.map.kpt
.....\..............\README
.....\raminfr.v
.....\simulation\modelsim\modelsim.ini
.....\..........\........\msim_transcript
.....\..........\........\rtl_work\raminfr\verilog.psm
.....\..........\........\........\.......\_primary.dat
.....\..........\........\........\.......\_primary.dbs
.....\..........\........\........\.......\_primary.vhd
.....\..........\........\........\testbench\verilog.psm
.....\..........\........\........\.........\_primary.dat
.....\..........\........\........\.........\_primary.dbs
.....\..........\........\........\.........\_primary.vhd
.....\..........\........\........\........._utilities\verilog.psm
.....\..........\........\........\...................\_primary.dat
.....\..........\........\........\...................\_primary.dbs
.....\..........\........\........\...................\_primary.vhd
.....\..........\........\........\....case\verilog.psm
.....\..........\........\........\........\_primary.dat
.....\..........\........\........\........\_primary.dbs
.....\..........\........\........\........\_primary.vhd
.....\..........\........\........\uart_debug_if\verilog.psm
.....\..........\........\........\.............\_primary.dat
.....\..........\........\........\.............\_primary.dbs
.....\..........\........\........\.............\_primary.vhd
.....\..........\........\........\.......vice\verilog.psm
.....\..........\........\........\...........\_primary.dat
.....\..........\........\........\...........\_primary.dbs
.....\..........\........\........\...........\_primary.vhd
.....\..........\........\........\..........._utilities\verilog.psm
.....\..........\........\........\.....................\_primary.dat
.....\..........\........\........\.....................\_primary.dbs
.....\..........\....
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