This procedure is based on Verilog HDL digital tube procedure, need can be downloaded.

seg7_verilog\db\prev_cmp_seg7.asm.qmsg
............\..\prev_cmp_seg7.eda.qmsg
............\..\prev_cmp_seg7.fit.qmsg
............\..\prev_cmp_seg7.map.qmsg
............\..\prev_cmp_seg7.qmsg
............\..\prev_cmp_seg7.sta.qmsg
............\..\prev_cmp_seg7.tan.qmsg
............\..\seg7.asm.qmsg
............\..\seg7.cbx.xml
............\..\seg7.cmp.bpm
............\..\seg7.cmp.cdb
............\..\seg7.cmp.ecobp
............\..\seg7.cmp.hdb
............\..\seg7.cmp.kpt
............\..\seg7.cmp.logdb
............\..\seg7.cmp.rdb
............\..\seg7.cmp0.ddb
............\..\seg7.cmp_merge.kpt
............\..\seg7.db_info
............\..\seg7.eco.cdb
............\..\seg7.eda.qmsg
............\..\seg7.fit.qmsg
............\..\seg7.hier_info
............\..\seg7.hif
............\..\seg7.lpc.html
............\..\seg7.lpc.rdb
............\..\seg7.lpc.txt
............\..\seg7.map.bpm
............\..\seg7.map.cdb
............\..\seg7.map.ecobp
............\..\seg7.map.hdb
............\..\seg7.map.kpt
............\..\seg7.map.logdb
............\..\seg7.map.qmsg
............\..\seg7.map_bb.cdb
............\..\seg7.map_bb.hdb
............\..\seg7.map_bb.logdb
............\..\seg7.pre_map.cdb
............\..\seg7.pre_map.hdb
............\..\seg7.rtlv.hdb
............\..\seg7.rtlv_sg.cdb
............\..\seg7.rtlv_sg_swap.cdb
............\..\seg7.sgdiff.cdb
............\..\seg7.sgdiff.hdb
............\..\seg7.sld_design_entry.sci
............\..\seg7.sld_design_entry_dsc.sci
............\..\seg7.sta.qmsg
............\..\seg7.sta.rdb
............\..\seg7.sta_cmp.8_slow.tdb
............\..\seg7.syn_hier_info
............\..\seg7.tis_db_list.ddb
............\..\seg7_global_asgn_op.abo
............\incremental_db\compiled_partitions\seg7.root_partition.cmp.atm
............\..............\...................\seg7.root_partition.cmp.dfp
............\..............\...................\seg7.root_partition.cmp.hdbx
............\..............\...................\seg7.root_partition.cmp.kpt
............\..............\...................\seg7.root_partition.cmp.logdb
............\..............\...................\seg7.root_partition.cmp.rcf
............\..............\...................\seg7.root_partition.map.atm
............\..............\...................\seg7.root_partition.map.dpi
............\..............\...................\seg7.root_partition.map.hdbx
............\..............\...................\seg7.root_partition.map.kpt
............\..............\README
............\seg7.asm.rpt
............\seg7.cdf
............\seg7.done
............\seg7.dpf
............\seg7.eda.rpt
............\seg7.fit.rpt
............\seg7.fit.smsg
............\seg7.fit.summary
............\seg7.flow.rpt
............\seg7.map.rpt
............\seg7.map.summary
............\seg7.pin
............\seg7.pof
............\seg7.qpf
............\seg7.qsf
............\seg7.qws
............\seg7.sdc
............\seg7.sof
............\seg7.sta.rpt
............\seg7.sta.summary
............\seg7.tan.rpt
............\seg7.tan.summary
............\seg7.v
............\seg7.v.bak
............\seg7_assignment_defaults.qdf
............\.imulation\modelsim\altera_mf.v
............\..........\........\cyclone\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\verilog.asm
............\..........\........\.......\..........................................\_primary.dat
............\..........\........\.......\..........................................\_primary.vhd
............\..........\........\.......\..............m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n\verilog.asm
............\..........\........\.......\...............................................\_primary.dat
............\..........\........\.......\...............................................\_primary.vhd
............\..........\........\.......\...................m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n\verilog.asm
............\..........\........\.......\...........................................................\_primary.dat
............\..........\........\.......\......................................................

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