design a second-counting watch with Language VHDL and platform xilinx

watch_sc4\watch_sc4.ise
.........\test_watch.xwv
.........\test_watch.vhw
.........\test_watch.ant
.........\test_watch.tbw
.........\test_watch.jhd
.........\test_watch.tfw
.........\_xmsgs\netgen.xmsgs
.........\......\xst.xmsgs
.........\......\fuse.xmsgs
.........\......\vhpcomp.xmsgs
.........\watch_sc4.ise_ISE_Backup
.........\test_watch_gen.prj
.........\xilinxsim.ini
.........\test_watch_beh.prj
.........\test_watch_beh__vlog.prj
.........\test_watch_beh__vhdl.prj
.........\watch_sc.vhd
.........\watch_sc_summary.html
.........\watch_sc2_summary.html
.........\watch_sc2.prj
.........\xst\work\sub00\vhpl00.vho
.........\...\....\.....\vhpl01.vho
.........\...\....\hdllib.ref
.........\...\....\hdpdeps.ref
.........\...\dump.xst\watch_sc2.prj\ntrc.scr
.........\watch_sc2.xst
.........\watch_sc2.cmd_log
.........\watch_sc2.syr
.........\watch_sc2.lso
.........\watch_sc4.ntrc_log
.........\.lso
.........\netgen\synthesis\watch_sc2_synthesis.nlf
.........\......\.........\watch_sc2_synthesis.v
.........\test_watch_bencher.prj
.........\pepExtractor.prj
.........\test_watch.xwv_bak
.........\watch_sc2.stx
.........\watch_sc2_vhdl.prj
.........\watch_sc2.ngr
.........\watch_sc2.ngc
.........\isim\work\vlg0E\test__watch.bin
.........\....\....\hdllib.ref
.........\....\....\test__watch\test__watch.h
.........\....\....\...........\mingw\test__watch.obj
.........\....\....\...........\xsimtest__watch.cpp
.........\....\....\sub00\vhpl00.vho
.........\....\....\.....\vhpl01.vho
.........\....\....\watch_sc2\behavioral.h
.........\....\....\.........\mingw\behavioral.obj
.........\....\....\vlg2D\glbl.bin
.........\....\....\glbl\glbl.h
.........\....\....\....\mingw\glbl.obj
.........\....\....\hdpdeps.ref
.........\xst\dump.xst\watch_sc2.prj\ngx\opt
.........\...\........\.............\...\notopt
.........\...\........\.............\ngx
.........\isim\work\test__watch\mingw
.........\....\....\watch_sc2\mingw
.........\....\....\glbl\mingw
.........\xst\work\sub00
.........\...\dump.xst\watch_sc2.prj
.........\isim\work\vlg0E
.........\....\....\test__watch
.........\....\....\sub00
.........\....\....\watch_sc2
.........\....\....\vlg2D
.........\....\....\glbl
.........\xst\projnav.tmp
.........\...\work
.........\...\dump.xst
.........\netgen\synthesis
.........\isim\work
.........\_xmsgs
.........\xst
.........\netgen
.........\isim
watch_sc4

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