verilog hdl developed frequency meter, operating environment, the DE2-115 development board, modelsim simulation of the testbench. RTL-level code

fre
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...\clk_div.v.bak
...\count10.v
...\count10.v.bak
...\db
...\..\fre.ace_cmp.bpm
...\..\fre.ace_cmp.cdb
...\..\fre.ace_cmp.hdb
...\..\fre.amm.cdb
...\..\fre.analyze_file.qmsg
...\..\fre.asm.qmsg
...\..\fre.asm.rdb
...\..\fre.asm_labs.ddb
...\..\fre.cbx.xml
...\..\fre.cmp.bpm
...\..\fre.cmp.cdb
...\..\fre.cmp.hdb
...\..\fre.cmp.kpt
...\..\fre.cmp.logdb
...\..\fre.cmp.rdb
...\..\fre.cmp_merge.kpt
...\..\fre.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
...\..\fre.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
...\..\fre.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
...\..\fre.db_info
...\..\fre.eco.cdb
...\..\fre.fit.qmsg
...\..\fre.hier_info
...\..\fre.hif
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...\..\fre.lpc.html
...\..\fre.lpc.rdb
...\..\fre.lpc.txt
...\..\fre.map.bpm
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...\..\fre.map.kpt
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...\..\fre.map_bb.cdb
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...\..\fre.pre_map.cdb
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...\..\fre.rpp.qmsg
...\..\fre.rtlv.hdb
...\..\fre.rtlv_sg.cdb
...\..\fre.rtlv_sg_swap.cdb
...\..\fre.sgate.rvd
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...\..\fre.sgdiff.cdb
...\..\fre.sgdiff.hdb
...\..\fre.sld_design_entry.sci
...\..\fre.sld_design_entry_dsc.sci
...\..\fre.smart_action.txt
...\..\fre.sta.qmsg
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...\..\fre.tiscmp.fast_1200mv_0c.ddb
...\..\fre.tiscmp.slow_1200mv_0c.ddb
...\..\fre.tiscmp.slow_1200mv_85c.ddb
...\..\fre.tis_db_list.ddb
...\..\logic_util_heursitic.dat
...\..\prev_cmp_fre.qmsg
...\dff_16.v
...\fre.asm.rpt
...\fre.cdf
...\fre.done
...\fre.dpf
...\fre.fit.rpt
...\fre.fit.smsg
...\fre.fit.summary
...\fre.flow.rpt
...\fre.htm
...\fre.map.rpt
...\fre.map.smsg
...\fre.map.summary
...\fre.pin
...\fre.qpf
...\fre.qsf
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...\fre.sdc
...\fre.sof
...\fre.sta.rpt
...\fre.sta.summary
...\fre.v
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...\fre_ctrl.v
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...\fre_meter.asm.rpt
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...\fre_meter.dpf
...\fre_meter.eda.rpt
...\fre_meter.fit.rpt
...\fre_meter.fit.smsg
...\fre_meter.fit.summary
...\fre_meter.flow.rpt

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