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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 427kb
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Introduction - If you have any usage issues, please Google them yourself
password lock FPGA-based design of the electronic code lock is a small digital system. It has many unique advantages:good privacy and security , it do not need the key but remember password to unlock, and so on while it compare to ordinary mechanical locks. At present, the electronic code lock is most used of SCM technology .In practice, however, the process easy run to fly. So the reliability of this system is poor. The paper introduced a field programmable gate arrays FPGA devices to design electronic password lock. The VHDL language is used to describe the system and achieved in EP3C10E144C8.
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电子密码锁程序设计与仿真实验\e_latch\e_latch(FANGZHEN).vwf
............................\.......\e_latch.acf
............................\.......\e_latch.asm.rpt
............................\.......\e_latch.cdf
............................\.......\e_latch.done
............................\.......\e_latch.dpf
............................\.......\e_latch.fit.rpt
............................\.......\e_latch.fit.smsg
............................\.......\e_latch.fit.summary
............................\.......\e_latch.flow.rpt
............................\.......\e_latch.hif
............................\.......\e_latch.map.rpt
............................\.......\e_latch.map.summary
............................\.......\e_latch.mmf
............................\.......\e_latch.pin
............................\.......\e_latch.pof
............................\.......\e_latch.qpf
............................\.......\e_latch.qsf
............................\.......\e_latch.qws
............................\.......\e_latch.sim.rpt
............................\.......\e_latch.sof
............................\.......\e_latch.tan.rpt
............................\.......\e_latch.tan.summary
............................\.......\e_latch.vhd
............................\.......\e_latch.vwf
............................\.......\db\e_latch.asm.qmsg
............................\.......\..\e_latch.cbx.xml
............................\.......\..\e_latch.cmp.cdb
............................\.......\..\e_latch.cmp.hdb
............................\.......\..\e_latch.cmp.logdb
............................\.......\..\e_latch.cmp.rdb
............................\.......\..\e_latch.cmp.tdb
............................\.......\..\e_latch.cmp0.ddb
............................\.......\..\e_latch.dbp
............................\.......\..\e_latch.db_info
............................\.......\..\e_latch.eco.cdb
............................\.......\..\e_latch.fit.qmsg
............................\.......\..\e_latch.hier_info
............................\.......\..\e_latch.hif
............................\.......\..\e_latch.map.cdb
............................\.......\..\e_latch.map.hdb
............................\.......\..\e_latch.map.logdb
............................\.......\..\e_latch.map.qmsg
............................\.......\..\e_latch.pre_map.cdb
............................\.......\..\e_latch.pre_map.hdb
............................\.......\..\e_latch.psp
............................\.......\..\e_latch.rtlv.hdb
............................\.......\..\e_latch.rtlv_sg.cdb
............................\.......\..\e_latch.rtlv_sg_swap.cdb
............................\.......\..\e_latch.sgdiff.cdb
............................\.......\..\e_latch.sgdiff.hdb
............................\.......\..\e_latch.sld_design_entry.sci
............................\.......\..\e_latch.sld_design_entry_dsc.sci
............................\.......\..\e_latch.syn_hier_info
............................\.......\..\e_latch.tan.qmsg
............................\.......\..\wed.zsf
............................\EDA设计电子密码锁程序设计与仿真实验.doc
............................\实训心得 别少东.doc
............................\e_latch\db
............................\e_latch
电子密码锁程序设计与仿真实验
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