The architecture DE2_70_TV and DE2_70_D5M_LTM very similar, as a frame buffer, so coupled with the algorithm to, basically on the SDRAM before doing the pre-treatment or post-processed on the SDRAM to SDRAM.

DE2_70_TV_sobel\hardware\Sdram_Control_4Port\Sdram_Params.h
...............\........\...................\Sdram_PLL.bsf
...............\........\...................\Sdram_PLL.ppf
...............\DE2_70_TV.qpf
...............\DE2_70_TV.qsf
...............\DE2_70_TV.qws
...............\release\DE2_70_TV.sof
...............\hardware\AUDIO_DAC.v
...............\........\Sdram_Control_4Port\command.v
...............\........\...................\control_interface.v
...............\........\DE2_70_TV.v
...............\........\DIV.v
...............\........\I2C_AV_Config.v
...............\........\I2C_Controller.v
...............\........\ITU_656_Decoder.v
...............\Sobel\LineBuffer_3.v
...............\hardware\Line_Buffer.v
...............\........\MAC_3.v
...............\Sobel\MAC_sobel.v
...............\.....\PA_3.v
...............\hardware\PLL.v
...............\........\Reset_Delay.v
...............\........\Sdram_Control_4Port\Sdram_Control_4Port.v
...............\........\...................\Sdram_PLL.v
...............\........\...................\Sdram_RD_FIFO.v
...............\........\...................\Sdram_WR_FIFO.v
...............\........\...................\sdr_data_path.v
...............\........\SEG7_LUT.v
...............\........\SEG7_LUT_8.v
...............\Sobel\Sobel.v
...............\.....\SQRT.v
...............\hardware\TD_Detect.v
...............\........\TP_RAM.v
...............\........\VGA_Ctrl.v
...............\........\YCbCr2RGB.v
...............\........\YUV422_to_444.v
...............\Sobel
...............\release
...............\hardware\Sdram_Control_4Port
...............\hardware
...............\db
DE2_70_TV_sobel

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