Double port ROM verilog realization, based on the development of the Actel development platform

Two_Port_RAM\Two Port RAM实验例程.pdf
............\...PortRAM\designer\impl1\designer.log
............\..........\........\.....\tp_ram_top\projectData\tp_ram_top.stp
............\..........\........\.....\..........\tp_ram_top.log
............\..........\........\.....\..........\tp_ram_top.pro
............\..........\........\.....\tp_ram_top.adb
............\..........\........\.....\...........dtf\verify.log
............\..........\........\.....\tp_ram_top.ide_des
............\..........\........\.....\tp_ram_top.stp
............\..........\........\.....\tp_ram_top.tcl
............\..........\hdl\ctrl_RAM.v
............\..........\...\hdlsynchk.tcl
............\..........\...\rec.v
............\..........\...\send.v
............\..........\...\tp_ram_top.v
............\..........\simulation\meminit.dat
............\..........\..........\modelsim.ini
............\..........\..........\modelsim.ini.sav
............\..........\..........\ram25608_R0C0.mem
............\..........\.martgen\ram25608\ram25608.cxf
............\..........\........\........\ram25608.gen
............\..........\........\........\ram25608.log
............\..........\........\........\ram25608.shx
............\..........\........\........\ram25608.v
............\..........\........\........\ram25608_R0C0.mem
............\..........\........\ram25608_work.ixf
............\..........\........\smartgen.aws
............\..........\.ynthesis\.recordref
............\..........\.........\stdout.log
............\..........\.........\.yntmp\sap.log
............\..........\.........\......\tp_ram_top.msg
............\..........\.........\......\tp_ram_top.plg
............\..........\.........\......\tp_ram_top_flink.htm
............\..........\.........\......\tp_ram_top_srr.htm
............\..........\.........\......\tp_ram_top_toc.htm
............\..........\.........\tp_ram_top.areasrr
............\..........\.........\tp_ram_top.edn
............\..........\.........\tp_ram_top.fse
............\..........\.........\tp_ram_top.htm
............\..........\.........\tp_ram_top.map
............\..........\.........\tp_ram_top.sap
............\..........\.........\tp_ram_top.sdf
............\..........\.........\tp_ram_top.srd
............\..........\.........\tp_ram_top.srm
............\..........\.........\tp_ram_top.srr
............\..........\.........\tp_ram_top.srs
............\..........\.........\tp_ram_top.tlg
............\..........\.........\tp_ram_top_sdc.sdc
............\..........\.........\tp_ram_top_syn.prj
............\..........\.........\traplog.tlg
............\..........\TwoPortRAM.prj
............\..........\TwoPortRAM.prj.convert.7.3.bak
............\..........\viewdraw\vf\project.lst
............\..........\........\viewdraw.ini
............\Two_Port_RAM_lab.rar
............\...PortRAM\designer\impl1\tp_ram_top\projectData
............\..........\........\.....\simulation
............\..........\........\.....\tp_ram_top
............\..........\........\.....\tp_ram_top.dtf
............\..........\........\impl1
............\..........\smartgen\ram25608
............\..........\.ynthesis\syntmp
............\..........\viewdraw\sch
............\..........\........\sym
............\..........\........\vf
............\..........\........\wir
............\..........\component
............\..........\constraint
............\..........\coreconsole
............\..........\designer
............\..........\hdl
............\..........\phy_synthesis
............\..........\simulation
............\..........\smartgen
............\..........\stimulus
............\..........\synthesis
............\..........\viewdraw
............\TwoPortRAM
Two_Port_RAM

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