DE2 development board LCD stopwatch program written in VHDL

DE2_lcd_clk
...........\db
...........\..\DE2_Clock.asm.qmsg
...........\..\DE2_Clock.asm_labs.ddb
...........\..\DE2_Clock.cbx.xml
...........\..\DE2_Clock.cmp.cdb
...........\..\DE2_Clock.cmp.hdb
...........\..\DE2_Clock.cmp.logdb
...........\..\DE2_Clock.cmp.rdb
...........\..\DE2_Clock.cmp.tdb
...........\..\DE2_Clock.cmp0.ddb
...........\..\DE2_Clock.db_info
...........\..\DE2_Clock.eco.cdb
...........\..\DE2_Clock.fit.qmsg
...........\..\DE2_Clock.hier_info
...........\..\DE2_Clock.hif
...........\..\DE2_Clock.map.cdb
...........\..\DE2_Clock.map.hdb
...........\..\DE2_Clock.map.logdb
...........\..\DE2_Clock.map.qmsg
...........\..\DE2_Clock.pre_map.cdb
...........\..\DE2_Clock.pre_map.hdb
...........\..\DE2_Clock.rtlv.hdb
...........\..\DE2_Clock.rtlv_sg.cdb
...........\..\DE2_Clock.rtlv_sg_swap.cdb
...........\..\DE2_Clock.sgdiff.cdb
...........\..\DE2_Clock.sgdiff.hdb
...........\..\DE2_Clock.signalprobe.cdb
...........\..\DE2_Clock.sld_design_entry.sci
...........\..\DE2_Clock.sld_design_entry_dsc.sci
...........\..\DE2_Clock.smp_dump.txt
...........\..\DE2_Clock.syn_hier_info
...........\..\DE2_Clock.tan.qmsg
...........\..\DE2_Clock.tis_db_list.ddb
...........\..\DE2_Clock.tmw_info
...........\DE2_Clock.asm.rpt
...........\DE2_CLOCK.cdf
...........\DE2_Clock.done
...........\DE2_Clock.dpf
...........\DE2_Clock.fit.eqn
...........\DE2_Clock.fit.rpt
...........\DE2_Clock.fit.smsg
...........\DE2_Clock.fit.summary
...........\DE2_Clock.flow.rpt
...........\DE2_Clock.map.eqn
...........\DE2_Clock.map.rpt
...........\DE2_Clock.map.summary
...........\DE2_Clock.pin
...........\DE2_Clock.pof
...........\DE2_Clock.qpf
...........\DE2_Clock.qsf
...........\DE2_Clock.qws
...........\DE2_CLOCK.sof
...........\DE2_Clock.tan.rpt
...........\DE2_Clock.tan.summary
...........\DE2_CLOCK.vhd
...........\DE2_CLOCK.vwf
...........\DE2_Clock_assignment_defaults.qdf

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