compare A and B,if equal ,output equal one

compare\compare.cr.mti
.......\compare.mpf
.......\compare.v
.......\compare.xml
.......\compare_tb.v
.......\compare_tb.v.bak
.......\modelsim.ini
.......\vsim.wlf
.......\work\@_opt\vopt25k4kw
.......\....\.....\vopt2ki2mw
.......\....\.....\vopt65w141
.......\....\.....\vopt97zyxh
.......\....\.....\voptdqkvxh
.......\....\.....\voptk6yiyh
.......\....\.....\voptqadc8y
.......\....\.....\voptqnjeyh
.......\....\.....\vopttt288y
.......\....\.....\voptvrqbrq
.......\....\.....\voptyar58y
.......\....\.....\_deps
.......\....\compare\verilog.asm
.......\....\.......\verilog.rw
.......\....\.......\_primary.dat
.......\....\.......\_primary.dbs
.......\....\.......\_primary.vhd
.......\....\......._tb\verilog.asm
.......\....\..........\verilog.rw
.......\....\..........\_primary.dat
.......\....\..........\_primary.dbs
.......\....\..........\_primary.vhd
.......\....\_info
.......\....\_vmake
.......\....\@_opt
.......\....\compare
.......\....\compare_tb
.......\....\_temp
.......\work
compare

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