Small VHDL CPU,as a example for developing CPU. It is simulated by Modelsim.

test_cpu\cpu.bsf
........\cpu.vhd
........\cpu.vhd.bak
........\cpu.vwf
........\cpu_struc.vhd
........\cpu_struc.vhd.bak
........\db\add_sub_4rh.tdf
........\..\add_sub_knh.tdf
........\..\add_sub_lnh.tdf
........\..\mux_1hc.tdf
........\..\prev_cmp_test_cpu.qmsg
........\..\prev_cmp_top.asm.qmsg
........\..\prev_cmp_top.eda.qmsg
........\..\prev_cmp_top.fit.qmsg
........\..\prev_cmp_top.map.qmsg
........\..\prev_cmp_top.sim.qmsg
........\..\prev_cmp_top.sta.qmsg
........\..\prev_cmp_top.tan.qmsg
........\..\test_cpu.smp_dump.txt
........\..\top.analyze_file.qmsg
........\..\top.asm.qmsg
........\..\top.cbx.xml
........\..\top.cmp.kpt
........\..\top.cmp.rdb
........\..\top.db_info
........\..\top.eco.cdb
........\..\top.eda.qmsg
........\..\top.eds_overflow
........\..\top.fit.qmsg
........\..\top.fnsim.hdb
........\..\top.fnsim.qmsg
........\..\top.hier_info
........\..\top.hif
........\..\top.lpc.html
........\..\top.lpc.rdb
........\..\top.lpc.txt
........\..\top.map.cdb
........\..\top.map.hdb
........\..\top.map.logdb
........\..\top.map.qmsg
........\..\top.pre_map.cdb
........\..\top.pre_map.hdb
........\..\top.rtlv.hdb
........\..\top.rtlv_sg.cdb
........\..\top.rtlv_sg_swap.cdb
........\..\top.sgdiff.cdb
........\..\top.sgdiff.hdb
........\..\top.sim.cvwf
........\..\top.sim.qmsg
........\..\top.sim.rdb
........\..\top.simfam
........\..\top.sim_ori.vwf
........\..\top.sld_design_entry.sci
........\..\top.sld_design_entry_dsc.sci
........\..\top.sta.qmsg
........\..\top.sta.rdb
........\..\top.syn_hier_info
........\..\top.tan.qmsg
........\..\top.tis_db_list.ddb
........\..\top.tmw_info
........\..\wed.wsf
........\incremental_db\compiled_partitions\top.db_info
........\..............\...................\top.root_partition.map.atm
........\..............\...................\top.root_partition.map.dpi
........\..............\...................\top.root_partition.map.hdbx
........\..............\...................\top.root_partition.map.kpt
........\..............\README
........\rom.bsf
........\rom.vhd
........\rom.vhd.bak
........\rom.vwf
........\rom_struc.vhd
........\rom_struc.vhd.bak
........\simulation\modelsim\modelsim.ini
........\..........\........\msim_transcript
........\..........\........\rtl_work\cpu\struc.dat
........\..........\........\........\...\struc.dbs
........\..........\........\........\...\struc.prw
........\..........\........\........\...\struc.psm
........\..........\........\........\...\_primary.dat
........\..........\........\........\...\_primary.dbs
........\..........\........\........\rom\struc.dat
........\..........\........\........\...\struc.dbs
........\..........\........\........\...\struc.prw
........\..........\........\........\...\struc.psm
........\..........\........\........\...\_primary.dat
........\..........\........\........\...\_primary.dbs
........\..........\........\........\top\struc.dat
........\..........\........\........\...\struc.dbs
........\..........\........\........\...\struc.prw
........\..........\........\........\...\struc.psm
........\..........\........\........\...\_primary.dat
........\..........\........\........\...\_primary.dbs
........\..........\........\........\..._vhd_tst\top_arch.dat
........\..........\........\........\...........\top_arch.dbs
........\..........\........\........\...........\top_arch.prw
........\..........\........\........\...........\top_arch.psm
........\..........\........\........\...........\_primary.dat
........\..........\........\........\...........\_primary.dbs
........\..........\........\........\_info

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