vhdl implementation of logic signal analyzer using fpga

synth_s3e new
..............\.lso
..............\capture_module.vhd
..............\clk_divider.vhd
..............\communication_module.vhd
..............\counter.vhd
..............\count_trigger_logic.vhd
..............\default.ipf
..............\default.ipf_ISE_Backup
..............\device_usage_statistics.html
..............\event_trigger_logic.vhd
..............\fifo.vhd
..............\fifomem.vhd
..............\lsa.cel
..............\lsa.ucf
..............\lsa_syn_top.bgn
..............\lsa_syn_top.bit
..............\lsa_syn_top.bld
..............\lsa_syn_top.cmd_log
..............\lsa_syn_top.drc
..............\lsa_syn_top.lso
..............\lsa_syn_top.ncd
..............\lsa_syn_top.ngc
..............\lsa_syn_top.ngd
..............\lsa_syn_top.ngr
..............\lsa_syn_top.pad
..............\lsa_syn_top.par
..............\lsa_syn_top.pcf
..............\lsa_syn_top.prj
..............\lsa_syn_top.stx
..............\lsa_syn_top.syr
..............\lsa_syn_top.twr
..............\lsa_syn_top.twx
..............\lsa_syn_top.unroutes
..............\lsa_syn_top.ut
..............\lsa_syn_top.vhd
..............\lsa_syn_top.xpi
..............\lsa_syn_top.xst
..............\lsa_syn_top_guide.ncd
..............\lsa_syn_top_map.map
..............\lsa_syn_top_map.mrp
..............\lsa_syn_top_map.ncd
..............\lsa_syn_top_map.ngm
..............\lsa_syn_top_pad.csv
..............\lsa_syn_top_pad.txt
..............\lsa_syn_top_prev_built.ngd
..............\lsa_syn_top_summary.html
..............\lsa_syn_top_summary.xml
..............\lsa_syn_top_usage.xml
..............\lsa_syn_top_vhdl.prj
..............\lsa_top.vhd
..............\match_trigger_logic.vhd
..............\match_unit.vhd
..............\pepExtractor.prj
..............\rptr_empty.vhd
..............\select_unit.vhd
..............\state_machine.vhd
..............\sync_r2w.vhd
..............\sync_w2r.vhd
..............\synth_s3e.ise
..............\synth_s3e.ise_ISE_Backup
..............\synth_s3e.ntrc_log
..............\synth_s3e.restore
..............\tb_capture_module.vhd
..............\tb_communication_module.vhd
..............\tb_fifo.vhd
..............\tb_lsa_syn_top.vhd
..............\tb_lsa_top.vhd
..............\tb_match_unit.vhd
..............\tb_uart.vhd
..............\uart.vhd
..............\uart_tx.vhd
..............\wptr_full.vhd
..............\xst
..............\...\dump.xst
..............\...\........\lsa_syn_top.prj
..............\...\........\...............\ngx
..............\...\........\...............\...\notopt
..............\...\........\...............\...\opt
..............\...\........\...............\ntrc.scr
..............\...\file graph
..............\...\projnav.tmp
..............\...\work
..............\...\....\hdllib.ref
..............\...\....\hdpdeps.ref
..............\...\....\sub00
..............\...\....\.....\vhpl00.vho
..............\...\....\.....\vhpl01.vho
..............\...\....\.....\vhpl02.vho
..............\...\....\.....\vhpl03.vho
..............\...\....\.....\vhpl04.vho
..............\...\....\.....\vhpl05.vho
..............\...\....\.....\vhpl06.vho
..............\...\....\.....\vhpl07.vho
..............\...\....\.....\vhpl08.vho
..............\...\....\.....\vhpl09.vho
..............\...\....\.....\vhpl10.vho
..............\...\....\.....\vhpl11.vho
..............\...\....\.....\vhpl12.vho
..............\...\....\.....\vhpl13.vho

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