This I learn when the original code FPGA in person, the realization of 8 x8 is the fifo structure, the synchronization of the fifo structure, the simulation test is a success!

FIFO\db\FIFO_8X8.asm.qmsg
....\..\FIFO_8X8.asm.rdb
....\..\FIFO_8X8.asm_labs.ddb
....\..\FIFO_8X8.cbx.xml
....\..\FIFO_8X8.cmp.bpm
....\..\FIFO_8X8.cmp.cdb
....\..\FIFO_8X8.cmp.ecobp
....\..\FIFO_8X8.cmp.hdb
....\..\FIFO_8X8.cmp.kpt
....\..\FIFO_8X8.cmp.logdb
....\..\FIFO_8X8.cmp.rdb
....\..\FIFO_8X8.cmp.tdb
....\..\FIFO_8X8.cmp0.ddb
....\..\FIFO_8X8.cmp2.ddb
....\..\FIFO_8X8.cmp_merge.kpt
....\..\FIFO_8X8.db_info
....\..\FIFO_8X8.eco.cdb
....\..\FIFO_8X8.eda.qmsg
....\..\FIFO_8X8.fit.qmsg
....\..\FIFO_8X8.hier_info
....\..\FIFO_8X8.hif
....\..\FIFO_8X8.lpc.html
....\..\FIFO_8X8.lpc.rdb
....\..\FIFO_8X8.lpc.txt
....\..\FIFO_8X8.map.bpm
....\..\FIFO_8X8.map.cdb
....\..\FIFO_8X8.map.ecobp
....\..\FIFO_8X8.map.hdb
....\..\FIFO_8X8.map.kpt
....\..\FIFO_8X8.map.logdb
....\..\FIFO_8X8.map.qmsg
....\..\FIFO_8X8.map_bb.cdb
....\..\FIFO_8X8.map_bb.hdb
....\..\FIFO_8X8.map_bb.logdb
....\..\FIFO_8X8.pre_map.cdb
....\..\FIFO_8X8.pre_map.hdb
....\..\FIFO_8X8.rpp.qmsg
....\..\FIFO_8X8.rtlv.hdb
....\..\FIFO_8X8.rtlv_sg.cdb
....\..\FIFO_8X8.rtlv_sg_swap.cdb
....\..\FIFO_8X8.sgate.rvd
....\..\FIFO_8X8.sgate_sm.rvd
....\..\FIFO_8X8.sgdiff.cdb
....\..\FIFO_8X8.sgdiff.hdb
....\..\FIFO_8X8.sld_design_entry.sci
....\..\FIFO_8X8.sld_design_entry_dsc.sci
....\..\FIFO_8X8.smart_action.txt
....\..\FIFO_8X8.syn_hier_info
....\..\FIFO_8X8.tan.qmsg
....\..\FIFO_8X8.tis_db_list.ddb
....\..\FIFO_8X8.tmw_info
....\..\logic_util_heursitic.dat
....\..\prev_cmp_FIFO_8X8.asm.qmsg
....\..\prev_cmp_FIFO_8X8.eda.qmsg
....\..\prev_cmp_FIFO_8X8.fit.qmsg
....\..\prev_cmp_FIFO_8X8.map.qmsg
....\..\prev_cmp_FIFO_8X8.qmsg
....\..\prev_cmp_FIFO_8X8.tan.qmsg
....\FIFO_8X8.asm.rpt
....\FIFO_8X8.done
....\FIFO_8X8.eda.rpt
....\FIFO_8X8.fit.rpt
....\FIFO_8X8.fit.summary
....\FIFO_8X8.flow.rpt
....\FIFO_8X8.map.rpt
....\FIFO_8X8.map.smsg
....\FIFO_8X8.map.summary
....\FIFO_8X8.pin
....\FIFO_8X8.pof
....\FIFO_8X8.qpf
....\FIFO_8X8.qsf
....\FIFO_8X8.qws
....\FIFO_8X8.sof
....\FIFO_8X8.tan.rpt
....\FIFO_8X8.tan.summary
....\FIFO_8X8.V
....\FIFO_8X8.V.bak
....\FIFO_8X8_nativelink_simulation.rpt
....\incremental_db\compiled_partitions\FIFO_8X8.root_partition.cmp.cdb
....\..............\...................\FIFO_8X8.root_partition.cmp.dfp
....\..............\...................\FIFO_8X8.root_partition.cmp.hdb
....\..............\...................\FIFO_8X8.root_partition.cmp.kpt
....\..............\...................\FIFO_8X8.root_partition.cmp.logdb
....\..............\...................\FIFO_8X8.root_partition.cmp.rcfdb
....\..............\...................\FIFO_8X8.root_partition.cmp.re.rcfdb
....\..............\...................\FIFO_8X8.root_partition.map.cdb
....\..............\...................\FIFO_8X8.root_partition.map.dpi
....\..............\...................\FIFO_8X8.root_partition.map.hdb
....\..............\...................\FIFO_8X8.root_partition.map.kpt
....\..............\README
....\simulation\modelsim\FIFO_8X8.sft
....\..........\........\FIFO_8X8.vo
....\..........\........\FIFO_8X8.vt
....\..........\........\FIFO_8X8.vt.bak
....\..........\........\FIFO_8X8_modelsim.xrf
....\..........\........\FIFO_8X8_run_msim_rtl_verilog.do
....\..........\........\FIFO_8X8_run_msim_rtl_verilog.do.bak
....\..........\........\FIFO_8X8_run_msim_rtl_verilog.do.bak1
....\..........\........\FIFO_8X8_run_msim_rtl_verilog.do.bak10
....\..........\........\FIFO_8X8_run_msim_rtl_verilog.do.bak2

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