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dianzizhong

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 820kb
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  • Author :刘****
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Introduction - If you have any usage issues, please Google them yourself
FPGA implementation of multi-function electronic clock procedures, including brightness adjustment, the reality and adjustment of the time and date, alarm clock and stopwatch
Packet file list
(Preview for download)
dianzizhong\alarm.vhd
...........\clock.vhd
...........\db\add_sub_3dc.tdf
...........\..\add_sub_4dc.tdf
...........\..\add_sub_59c.tdf
...........\..\add_sub_5dc.tdf
...........\..\add_sub_69c.tdf
...........\..\add_sub_6dc.tdf
...........\..\add_sub_7dc.tdf
...........\..\add_sub_8dc.tdf
...........\..\add_sub_9dc.tdf
...........\..\add_sub_a9c.tdf
...........\..\add_sub_adc.tdf
...........\..\add_sub_bdc.tdf
...........\..\alt_u_div_2oe.tdf
...........\..\alt_u_div_4oe.tdf
...........\..\alt_u_div_ioe.tdf
...........\..\dianzizhong.asm.qmsg
...........\..\dianzizhong.cbx.xml
...........\..\dianzizhong.cmp.bpm
...........\..\dianzizhong.cmp.cdb
...........\..\dianzizhong.cmp.ecobp
...........\..\dianzizhong.cmp.hdb
...........\..\dianzizhong.cmp.logdb
...........\..\dianzizhong.cmp.rdb
...........\..\dianzizhong.cmp.tdb
...........\..\dianzizhong.cmp0.ddb
...........\..\dianzizhong.cmp_bb.cdb
...........\..\dianzizhong.cmp_bb.hdb
...........\..\dianzizhong.cmp_bb.logdb
...........\..\dianzizhong.cmp_bb.rcf
...........\..\dianzizhong.dbp
...........\..\dianzizhong.db_info
...........\..\dianzizhong.eco.cdb
...........\..\dianzizhong.fit.qmsg
...........\..\dianzizhong.hier_info
...........\..\dianzizhong.hif
...........\..\dianzizhong.map.bpm
...........\..\dianzizhong.map.cdb
...........\..\dianzizhong.map.ecobp
...........\..\dianzizhong.map.hdb
...........\..\dianzizhong.map.logdb
...........\..\dianzizhong.map.qmsg
...........\..\dianzizhong.map_bb.cdb
...........\..\dianzizhong.map_bb.hdb
...........\..\dianzizhong.map_bb.logdb
...........\..\dianzizhong.merge.qmsg
...........\..\dianzizhong.pre_map.cdb
...........\..\dianzizhong.pre_map.hdb
...........\..\dianzizhong.psp
...........\..\dianzizhong.pss
...........\..\dianzizhong.rtlv.hdb
...........\..\dianzizhong.rtlv_sg.cdb
...........\..\dianzizhong.rtlv_sg_swap.cdb
...........\..\dianzizhong.sgdiff.cdb
...........\..\dianzizhong.sgdiff.hdb
...........\..\dianzizhong.signalprobe.cdb
...........\..\dianzizhong.sld_design_entry.sci
...........\..\dianzizhong.sld_design_entry_dsc.sci
...........\..\dianzizhong.syn_hier_info
...........\..\dianzizhong.tan.qmsg
...........\..\lpm_divide_d5m.tdf
...........\..\lpm_divide_e5m.tdf
...........\..\lpm_divide_l5m.tdf
...........\..\sign_div_unsign_9kh.tdf
...........\..\sign_div_unsign_akh.tdf
...........\..\sign_div_unsign_hkh.tdf
...........\dianzizhong.asm.rpt
...........\dianzizhong.cdf
...........\dianzizhong.done
...........\dianzizhong.dpf
...........\dianzizhong.fit.rpt
...........\dianzizhong.fit.smsg
...........\dianzizhong.fit.summary
...........\dianzizhong.flow.rpt
...........\dianzizhong.map.rpt
...........\dianzizhong.map.summary
...........\dianzizhong.merge.rpt
...........\dianzizhong.pin
...........\dianzizhong.pof
...........\dianzizhong.qpf
...........\dianzizhong.qsf
...........\dianzizhong.qws
...........\dianzizhong.sof
...........\dianzizhong.tan.rpt
...........\dianzizhong.tan.summary
...........\dianzizhong.vhd
...........\disply.vhd
...........\dvf2.vhd
...........\scan_led2.vhd
...........\second_clock.vhd
...........\db
dianzizhong
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