A SPI Master code edited by VHDL language,the SPI modul use 0 MODE(i.e CPOL=0,CPHA=0)to communicate with the SPI Slave.and there is a testbench in the file folder,which has been tested in Modelsim6.5,you can use it in FPGA directly.

spi主机程序
...........\spi_master.vhd
...........\spi_master_tb.vhd

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