Digital circuit and logic design using Quartus7.2 to design a cartoon by VHDL language.

dengkong\dengkong.qpf
........\dengkong.qsf
........\.b\wed.wsf
........\..\dengkong.db_info
........\..\dengkong.rtlv_sg_swap.cdb
........\..\dengkong.tis_db_list.ddb
........\..\dengkong.fit.qmsg
........\..\prev_cmp_dengkong.map.qmsg
........\..\dengkong.cmp.logdb
........\..\dengkong.cbx.xml
........\..\dengkong.pre_map.hdb
........\..\dengkong.smp_dump.txt
........\..\dengkong.pre_map.cdb
........\..\dengkong.asm.qmsg
........\..\dengkong.map.logdb
........\..\dengkong.tan.qmsg
........\..\prev_cmp_dengkong.qmsg
........\..\prev_cmp_dengkong.sim.qmsg
........\..\dengkong.map.qmsg
........\..\dengkong.rtlv_sg.cdb
........\..\prev_cmp_dengkong.fit.qmsg
........\..\prev_cmp_dengkong.asm.qmsg
........\..\dengkong.rtlv.hdb
........\..\dengkong.hif
........\..\prev_cmp_dengkong.tan.qmsg
........\..\dengkong.sim.qmsg
........\..\dengkong.hier_info
........\..\dengkong.sim.hdb
........\..\dengkong.sim.cvwf
........\..\dengkong.sim.rdb
........\..\dengkong.sgdiff.hdb
........\..\dengkong.eco.cdb
........\..\dengkong.psp
........\..\dengkong.pss
........\..\dengkong.dbp
........\..\dengkong.cmp.tdb
........\..\dengkong.sgdiff.cdb
........\..\dengkong.eds_overflow
........\..\dengkong.sld_design_entry_dsc.sci
........\..\dengkong.syn_hier_info
........\..\dengkong.map.cdb
........\..\dengkong.map.hdb
........\..\dengkong.cmp.hdb
........\..\dengkong.cmp.rdb
........\..\dengkong.cmp0.ddb
........\..\dengkong.cmp.cdb
........\..\dengkong.sld_design_entry.sci
........\dengkong.flow.rpt
........\dengkong.asm.rpt
........\dengkong.map.summary
........\dengkong.tan.rpt
........\dengkong.map.rpt
........\dengkong.fit.rpt
........\dengkong.sim.rpt
........\dengkong.vhd.bak
........\dengkong.vhd
........\dengkong.pin
........\dengkong.fit.summary
........\dengkong.qws
........\dengkong.tan.summary
........\dengkong.done
........\dengkong.vwf
........\db
dengkong

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