based on chinese descripion.

verilog_led_run\db\prev_cmp_verilog_led_run.asm.qmsg
...............\..\prev_cmp_verilog_led_run.eda.qmsg
...............\..\prev_cmp_verilog_led_run.fit.qmsg
...............\..\prev_cmp_verilog_led_run.map.qmsg
...............\..\prev_cmp_verilog_led_run.qmsg
...............\..\prev_cmp_verilog_led_run.tan.qmsg
...............\..\verilog_led_run.ace_cmp.bpm
...............\..\verilog_led_run.ace_cmp.cdb
...............\..\verilog_led_run.ace_cmp.ecobp
...............\..\verilog_led_run.ace_cmp.hdb
...............\..\verilog_led_run.asm.qmsg
...............\..\verilog_led_run.asm_labs.ddb
...............\..\verilog_led_run.cbx.xml
...............\..\verilog_led_run.cmp.bpm
...............\..\verilog_led_run.cmp.cdb
...............\..\verilog_led_run.cmp.ecobp
...............\..\verilog_led_run.cmp.hdb
...............\..\verilog_led_run.cmp.kpt
...............\..\verilog_led_run.cmp.logdb
...............\..\verilog_led_run.cmp.rdb
...............\..\verilog_led_run.cmp.tdb
...............\..\verilog_led_run.cmp0.ddb
...............\..\verilog_led_run.cmp2.ddb
...............\..\verilog_led_run.cmp_merge.kpt
...............\..\verilog_led_run.db_info
...............\..\verilog_led_run.eco.cdb
...............\..\verilog_led_run.eda.qmsg
...............\..\verilog_led_run.fit.qmsg
...............\..\verilog_led_run.hier_info
...............\..\verilog_led_run.hif
...............\..\verilog_led_run.lpc.html
...............\..\verilog_led_run.lpc.rdb
...............\..\verilog_led_run.lpc.txt
...............\..\verilog_led_run.map.bpm
...............\..\verilog_led_run.map.cdb
...............\..\verilog_led_run.map.ecobp
...............\..\verilog_led_run.map.hdb
...............\..\verilog_led_run.map.kpt
...............\..\verilog_led_run.map.logdb
...............\..\verilog_led_run.map.qmsg
...............\..\verilog_led_run.map_bb.cdb
...............\..\verilog_led_run.map_bb.hdb
...............\..\verilog_led_run.map_bb.logdb
...............\..\verilog_led_run.pre_map.cdb
...............\..\verilog_led_run.pre_map.hdb
...............\..\verilog_led_run.rtlv.hdb
...............\..\verilog_led_run.rtlv_sg.cdb
...............\..\verilog_led_run.rtlv_sg_swap.cdb
...............\..\verilog_led_run.sgdiff.cdb
...............\..\verilog_led_run.sgdiff.hdb
...............\..\verilog_led_run.sld_design_entry.sci
...............\..\verilog_led_run.sld_design_entry_dsc.sci
...............\..\verilog_led_run.syn_hier_info
...............\..\verilog_led_run.tan.qmsg
...............\..\verilog_led_run.tis_db_list.ddb
...............\..\verilog_led_run.tmw_info
...............\incremental_db\compiled_partitions\verilog_led_run.root_partition.cmp.atm
...............\..............\...................\verilog_led_run.root_partition.cmp.dfp
...............\..............\...................\verilog_led_run.root_partition.cmp.hdbx
...............\..............\...................\verilog_led_run.root_partition.cmp.kpt
...............\..............\...................\verilog_led_run.root_partition.cmp.logdb
...............\..............\...................\verilog_led_run.root_partition.cmp.rcf
...............\..............\...................\verilog_led_run.root_partition.map.atm
...............\..............\...................\verilog_led_run.root_partition.map.dpi
...............\..............\...................\verilog_led_run.root_partition.map.hdbx
...............\..............\...................\verilog_led_run.root_partition.map.kpt
...............\..............\README
...............\simulation\modelsim\modelsim.ini
...............\..........\........\msim_transcript
...............\..........\........\rtl_work\verilog_led_run\verilog.prw
...............\..........\........\........\...............\verilog.psm
...............\..........\........\........\...............\_primary.dat
...............\..........\........\........\...............\_primary.dbs
...............\..........\........\........\...............\_primary.vhd
...............\..........\........\........\..............._vlg_tst\verilog.prw
.............

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