xilinx FPGA IP Core

Nexys3_BSB_Support_v_2_4
........................\Nexys3_AXI_BSB_Support
........................\......................\lib
........................\......................\...\Digilent
........................\......................\...\........\boards
........................\......................\...\........\......\Digilent_Nexys3
........................\......................\...\........\......\...............\data
........................\......................\...\........\......\...............\....\BSB_Component.xml
........................\......................\...\........\......\...............\....\Ethernet_Lite_axi_ethernetlite_v_1_00.ucf
........................\......................\...\........\......\...............\....\nexys3.tcl
........................\......................\...\........\......\...............\....\nexys3.xml
........................\......................\...\........\......\...............\....\nexys3_pins.csv
........................\......................\...\........\pcores
........................\......................\...\........\......\d_qspi_axi_v1_00_a
........................\......................\...\........\......\..................\data
........................\......................\...\........\......\..................\....\d_qspi_axi_v2_1_0.mpd
........................\......................\...\........\......\..................\....\d_qspi_axi_v2_1_0.mui
........................\......................\...\........\......\..................\....\d_qspi_axi_v2_1_0.pao
........................\......................\...\........\......\..................\hdl
........................\......................\...\........\......\..................\...\verilog
........................\......................\...\........\......\..................\...\.......\spi_fifo_receive.v
........................\......................\...\........\......\..................\...\.......\spi_fifo_send.v
........................\......................\...\........\......\..................\...\.......\spi_sf.v
........................\......................\...\........\......\..................\...\.......\spi_tr8.v
........................\......................\...\........\......\..................\...\vhdl
........................\......................\...\........\......\..................\...\....\d_qspi_axi.vhd
........................\......................\...\........\......\..................\...\....\user_logic.vhd
........................\......................\...\........\......\d_usb_epp_dstm_axi_v1_00_a
........................\......................\...\........\......\..........................\data
........................\......................\...\........\......\..........................\....\d_usb_epp_dstm_axi_v2_1_0.mpd
........................\......................\...\........\......\..........................\....\d_usb_epp_dstm_axi_v2_1_0.mui
........................\......................\...\........\......\..........................\....\d_usb_epp_dstm_axi_v2_1_0.pao
........................\......................\...\........\......\..........................\hdl
........................\......................\...\........\......\..........................\...\verilog
........................\......................\...\........\......\..........................\...\.......\dstm.v
........................\......................\...\........\......\..........................\...\.......\epp_dstm_mux.v
........................\......................\...\........\......\..........................\...\.......\fifo.v
........................\......................\...\........\......\..........................\...\.......\usb_epp.v
........................\......................\...\........\......\..........................\...\.......\usb_epp_dstm.v
........................\......................\...\........\......\..........................\...\vhdl
........................\......................\...\........\......\..........................\

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