8 hardware addition the design of the counter has been verified on the test chamber.

ep1c12_9_adder8\adder8.asm.rpt
...............\adder8.bsf
...............\adder8.cdf
...............\adder8.done
...............\adder8.fit.eqn
...............\adder8.fit.rpt
...............\adder8.fit.summary
...............\adder8.flow.rpt
...............\adder8.map.eqn
...............\adder8.map.rpt
...............\adder8.map.summary
...............\adder8.pin
...............\adder8.pof
...............\adder8.qpf
...............\adder8.qsf
...............\adder8.qws
...............\adder8.sof
...............\adder8.tan.rpt
...............\adder8.tan.summary
...............\adder8.vhd
...............\Block1.bdf
...............\cmp_state.ini
...............\db\adder8.asm.qmsg
...............\..\adder8.cbx.xml
...............\..\adder8.cmp.cdb
...............\..\adder8.cmp.hdb
...............\..\adder8.cmp.rdb
...............\..\adder8.cmp.tdb
...............\..\adder8.cmp0.ddb
...............\..\adder8.db_info
...............\..\adder8.eco.cdb
...............\..\adder8.fit.qmsg
...............\..\adder8.hier_info
...............\..\adder8.hif
...............\..\adder8.map.cdb
...............\..\adder8.map.hdb
...............\..\adder8.map.qmsg
...............\..\adder8.pre_map.cdb
...............\..\adder8.pre_map.hdb
...............\..\adder8.psp
...............\..\adder8.rtlv.hdb
...............\..\adder8.rtlv_sg.cdb
...............\..\adder8.rtlv_sg_swap.cdb
...............\..\adder8.sgdiff.cdb
...............\..\adder8.sgdiff.hdb
...............\..\adder8.signalprobe.cdb
...............\..\adder8.sld_design_entry.sci
...............\..\adder8.sld_design_entry_dsc.sci
...............\..\adder8.syn_hier_info
...............\..\adder8.tan.qmsg
...............\..\adder8_cmp.qrpt
...............\..\_desktop.ini
...............\key_led.bsf
...............\key_led.vhd
...............\_desktop.ini
...............\db
ep1c12_9_adder8

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