VLYNQ TI dsp and XILINX fpga interface。

coregen
.......\ip
.......\..\xilinx
.......\..\......\network
.......\..\......\.......\com
.......\..\......\.......\...\xilinx
.......\..\......\.......\...\......\ip
.......\..\......\.......\...\......\..\vlynq_v1_2
.......\..\......\.......\...\......\..\..........\8b10bdec
.......\..\......\.......\...\......\..\..........\........\vlynq_xi_8b10b_dec.v
.......\..\......\.......\...\......\..\..........\8b10benc
.......\..\......\.......\...\......\..\..........\........\vlynq_xi_8b10b_enc.v
.......\..\......\.......\...\......\..\..........\analyze_order.txt
.......\..\......\.......\...\......\..\..........\bb_comps.class
.......\..\......\.......\...\......\..\..........\commadet
.......\..\......\.......\...\......\..\..........\........\vlynq_commadet.v
.......\..\......\.......\...\......\..\..........\copy_fixed_netlists.class
.......\..\......\.......\...\......\..\..........\doc
.......\..\......\.......\...\......\..\..........\...\vlynq_ds324.pdf
.......\..\......\.......\...\......\..\..........\...\vlynq_gsug171.pdf
.......\..\......\.......\...\......\..\..........\...\vlynq_v1_2_release_notes.txt
.......\..\......\.......\...\......\..\..........\...\vlynq_v1_2_vinfo.html
.......\..\......\.......\...\......\..\..........\fifo
.......\..\......\.......\...\......\..\..........\....\afifo36x32_preload0.v
.......\..\......\.......\...\......\..\..........\....\bfifo32x32_preload0.v
.......\..\......\.......\...\......\..\..........\glbl_v.class
.......\..\......\.......\...\......\..\..........\gui
.......\..\......\.......\...\......\..\..........\...\vlynq_v1_2.tcl
.......\..\......\.......\...\......\..\..........\...\vlynq_v1_2.ui
.......\..\......\.......\...\......\..\..........\implement_bat.class
.......\..\......\.......\...\......\..\..........\implement_sh.class
.......\..\......\.......\...\......\..\..........\netlists
.......\..\......\.......\...\......\..\..........\........\afifo36x32_preload0.ngc
.......\..\......\.......\...\......\..\..........\........\bfifo32x32_preload0.ngc
.......\..\......\.......\...\......\..\..........\........\vlynq_xi_8b10b_dec.edn
.......\..\......\.......\...\......\..\..........\........\vlynq_xi_8b10b_enc.edn
.......\..\......\.......\...\......\..\..........\opb_vbus
.......\..\......\.......\...\......\..\..........\........\opb_master.v
.......\..\......\.......\...\......\..\..........\........\opb_rstreg.v
.......\..\......\.......\...\......\..\..........\........\opb_slave.v
.......\..\......\.......\...\......\..\..........\simulate_mti_do_v.class
.......\..\......\.......\...\......\..\..........\simulate_mti_do_vhd.class
.......\..\......\.......\...\......\..\..........\simulate_mti_do_vhd_timing.class
.......\..\......\.......\...\......\..\..........\simulate_mti_do_v_timing.class
.......\..\......\.......\...\......\..\..........\simulate_ncsim_bat_v.class
.......\..\......\.......\...\......\..\..........\simulate_ncsim_bat_vhd.class
.......\..\......\.......\...\......\..\..........\simulate_ncsim_bat_vhd_timing.class
.......\..\......\.......\...\......\..\..........\simulate_ncsim_bat_v_timing.class
.......\..\......\.......\...\......\..\..........\simulate_ncsim_sh_v.class
.......\..\......\.......\...\......\..\..........\simulate_ncsim_sh_vhd.class
.......\..\......\.......\...\......\..\..........\simulate_ncsim_sh_vhd_timing.class
.......\..\......\.......\...\......\..\..........\simulate_ncsim_sh_v_timing.class
.......\..\......\.......\...\......\..\..........\vlynq.v
.......\..\......\.......\...\......\..\..........\vlynq_afifo.v
.......\..\......\.......\...\......\..\..........\vlynq_bfifo.v
.......\..\......\.......\...\......\..\..........\vlynq_clk_gen_v.class
.......\..\......\.......\...\......\..\..........\vlynq_clk_gen_vhd.class
.......\..\......\.......\...\......\..\..........\vlynq_crc.vhd
.......\..\......\.......\...\......\..\..........\vlynq_driver_v.class
.......\..\......\.......\...\......\..\..........\vlynq_driver_vhd.class
.......\..\......\.......\...\......\..\..........\vlynq_gen.vhd
.......\..\...

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