five level pipeline CPU written in Verilog.

PipelineCPU2\ALU.v
............\ALU.v.bak
............\ALU_tb.v
............\ALU_tb.v.bak
............\Decode.v
............\Decode.v.bak
............\DecodeSim.v
............\Decode_tb.v
............\Decode_tb.v.bak
............\EX.v
............\EX.v.bak
............\ID.v
............\ID.v.bak
............\IF.v
............\IF.v.bak
............\IF2.v
............\IF_tb.v
............\InstructionROM.v
............\InstructionROM.v.bak
............\lab28\.lso
............\.....\ALU.v
............\.....\DataRAM.asy
............\.....\DataRAM.ngc
............\.....\DataRAM.sym
............\.....\DataRAM.v
............\.....\DataRAM.veo
............\.....\DataRAM.vhd
............\.....\DataRAM.vho
............\.....\DataRAM.xco
............\.....\DataRAM_flist.txt
............\.....\DataRAM_readme.txt
............\.....\DataRAM_xmdf.tcl
............\.....\Decode.v
............\.....\DecodeSim.v
............\.....\EX.v
............\.....\ID.v
............\.....\IF.v
............\.....\InstructionROM.v
............\.....\lab28.ise
............\.....\lab28.ise_ISE_Backup
............\.....\lab28.ntrc_log
............\.....\lab28.restore
............\.....\mipspipelinecpu.bgn
............\.....\mipspipelinecpu.bit
............\.....\MipsPipelineCPU.bld
............\.....\MipsPipelineCPU.cmd_log
............\.....\mipspipelinecpu.drc
............\.....\MipsPipelineCPU.lso
............\.....\MipsPipelineCPU.ncd
............\.....\MipsPipelineCPU.ngc
............\.....\MipsPipelineCPU.ngd
............\.....\MipsPipelineCPU.ngr
............\.....\MipsPipelineCPU.pad
............\.....\MipsPipelineCPU.par
............\.....\MipsPipelineCPU.pcf
............\.....\MipsPipelineCPU.prj
............\.....\MipsPipelineCPU.stx
............\.....\MipsPipelineCPU.syr
............\.....\mipspipelinecpu.twr
............\.....\mipspipelinecpu.twx
............\.....\MipsPipelineCPU.unroutes
............\.....\MipsPipelineCPU.ut
............\.....\MipsPipelineCPU.v
............\.....\MipsPipelineCPU.xpi
............\.....\MipsPipelineCPU.xst
............\.....\MipsPipelineCPU_guide.ncd
............\.....\MipsPipelineCPU_map.map
............\.....\MipsPipelineCPU_map.mrp
............\.....\MipsPipelineCPU_map.ncd
............\.....\MipsPipelineCPU_map.ngm
............\.....\MipsPipelineCPU_pad.csv
............\.....\MipsPipelineCPU_pad.txt
............\.....\MipsPipelineCPU_prev_built.ngd
............\.....\MipsPipelineCPU_summary.html
............\.....\MipsPipelineCPU_summary.xml
............\.....\MipsPipelineCPU_usage.xml
............\.....\PipelineSIM.v
............\.....\reg32bit.v
............\.....\Registers.v
............\.....\templates\coregen.xml
............\.....\xst\dump.xst\MipsPipelineCPU.prj\ntrc.scr
............\.....\...\work\hdllib.ref
............\.....\...\....\vlg1E\_data_r_a_m.bin
............\.....\...\....\...20\_registers.bin
............\.....\...\....\....A\_a_l_u.bin
............\.....\...\....\....F\_mips_pipeline_c_p_u.bin
............\.....\...\....\...30\_decode.bin
............\.....\...\....\....1\_e_x.bin
............\.....\...\....\.....\_i_d.bin
............\.....\...\....\....3\_i_f.bin
............\.....\...\....\...7C\_instruction_r_o_m.bin
............\.....\_ngo\netlist.lst
............\.....\.xmsgs\bitgen.xmsgs
............\.....\......\map.xmsgs
............\.....\......\ngdbuild.xmsgs
............\.....\......\par.xmsgs
............\.....\......\trce.xmsgs
............\.....\......\xst.xmsgs
............\lab28.cr.mti
............\lab28.mpf

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