Original, achieves single-cycle MIPS processor Verilog source code, the FPGA, storage access instructions load word (lw) and store word (sw) arithmetic logic instructions add, addi, sub, and, or, and slt jump instructionbranch equal (beq, which) and jump (j)

MIPS处理器Verilog代码\Adder_PCShift.v
.....................\ALU.v
.....................\ALUOPUnit.v
.....................\CPU.v
.....................\CtrlUnit.v
.....................\DataMem.v
.....................\Expand.v
.....................\Inmemory.v
.....................\JpAD.v
.....................\MUX_32.v
.....................\MUX_5.v
.....................\PCAdder.v
.....................\PCCounter.v
.....................\Register.v
.....................\求最大公约数需要修改的模块\ALU.v
.....................\..........................\ALUOPUnit.v
.....................\..........................\Inmemory.v
.....................\..........................\Inmemory.v.bak
.....................\..........................\transcript
.....................\求最大公约数需要修改的模块
MIPS处理器Verilog代码

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