MIPS Pipelined CPU written on VHDL with commands, 5 stage pipeline

VHDL
....\adder.vhd
....\alu.vhd
....\Alu_control_signals.vhd
....\and_gate.vhd
....\arith_unit.vhd
....\control_signals.vhd
....\Counter_2bit.vhd
....\debug_memory_interface.v
....\Declaration_Package.vhd
....\Decoder_2bit.vhd
....\dual_port_ram_16k.vhd
....\dual_port_ram_4k.vhd
....\EMB_ADD_SUB.vhd
....\FF_1.vhd
....\FF_128.vhd
....\FF_32.vhd
....\flipflop.vhdl
....\full_adder.vhd
....\fwardunit.vhd
....\GlobalValue.vhd
....\half_adder.vhd
....\hazard_unit.vhd
....\logic_unit.vhd
....\MAC.vhd
....\MAC_UNIT.vhd
....\mips_5_stage_processor.vhd
....\multiplex.vhd
....\MULT_8x8.vhd
....\mux.vhd
....\mux2.vhd
....\MUX4_32.vhd
....\mux_3.vhd
....\MUX_32.vhd
....\mux_module.vhd
....\Nbitreg.vhdl
....\Nbit_adder.vhd
....\Nbit_and.vhd
....\Nbit_not.vhd
....\Nbit_or.vhd
....\Nbit_sub.vhd
....\not_gate.vhd
....\or_gate.vhd
....\out_sel.vhd
....\Parallel_add_16x4.vhd
....\pc_reg.vhd
....\reg.vhd
....\register_file.vhd
....\shift_left.vhd
....\signed_div.vhd
....\signed_mult.vhd
....\sign_ext.vhd
....\STAGE_EX.vhd
....\STAGE_ID.vhd
....\STAGE_IF.vhd
....\STAGE_MEM.vhd
....\STAGE_WB.vhd
....\status_register.vhd
....\top_level.pin
....\top_level.qpf
....\top_level.qsf
....\top_level.sof
....\top_level.vhd
Assembler code
..............\code.asm
..............\Program_Memory.hex
..............\Program_Memory.mif
Matlab Code
...........\4 times the width of the small.m
...........\correlacion.m
...........\image.bin
...........\template1.bin
...........\template2.bin
...........\template3.bin

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