Based on the QUTER ST device VHDL language design!

SR\cmp_state.ini
..\db\SR.asm.qmsg
..\..\SR.cbx.xml
..\..\SR.cmp.cdb
..\..\SR.cmp.hdb
..\..\SR.cmp.rdb
..\..\SR.cmp.tdb
..\..\SR.cmp0.ddb
..\..\SR.db_info
..\..\SR.eco.cdb
..\..\SR.eds_overflow
..\..\SR.fit.qmsg
..\..\SR.fnsim.cdb
..\..\SR.fnsim.hdb
..\..\SR.hier_info
..\..\SR.hif
..\..\SR.map.cdb
..\..\SR.map.hdb
..\..\SR.map.qmsg
..\..\SR.pre_map.cdb
..\..\SR.pre_map.hdb
..\..\SR.psp
..\..\SR.rtlv.hdb
..\..\SR.rtlv_sg.cdb
..\..\SR.rtlv_sg_swap.cdb
..\..\SR.sgdiff.cdb
..\..\SR.sgdiff.hdb
..\..\SR.signalprobe.cdb
..\..\SR.sim.hdb
..\..\SR.sim.qmsg
..\..\SR.sim.rdb
..\..\SR.sld_design_entry.sci
..\..\SR.sld_design_entry_dsc.sci
..\..\SR.syn_hier_info
..\..\SR.tan.qmsg
..\..\SR_cmp.qrpt
..\SR.asm.rpt
..\SR.bdf
..\SR.bsf
..\SR.done
..\SR.fit.eqn
..\SR.fit.rpt
..\SR.fit.summary
..\SR.flow.rpt
..\SR.map.eqn
..\SR.map.rpt
..\SR.map.summary
..\SR.pin
..\SR.pof
..\SR.qpf
..\SR.qsf
..\SR.qws
..\SR.sim.rpt
..\SR.tan.rpt
..\SR.tan.summary
..\SR.vwf
..\db
SR

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