A switchable clock divider divider verilog language, modify the parameters according to the specific circumstances of different sub-frequency

fangbo
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......\..............\compiled_partitions
......\..............\...................\fangbo.root_partition.cmp.atm
......\..............\...................\fangbo.root_partition.cmp.dfp
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......\..............\...................\fangbo.root_partition.cmp.rcf
......\..............\...................\fangbo.root_partition.map.atm
......\..............\...................\fangbo.root_partition.map.dpi
......\..............\...................\fangbo.root_partition.map.hdbx
......\..............\...................\fangbo.root_partition.map.kpt

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