FPGA-based PCI bus interface design

SOPC_PCI\.sopc_builder\filters.xml
........\adata.v
........\adcontrol.v
........\ad_busy.v
........\altpll0.bsf
........\altpll0.cmp
........\altpll0.v
........\altpll0_bb.v
........\bht_ram.mif
........\cmp_state.ini
........\cpu.ocp
........\cpu.v
........\cpu_jtag_debug_module.v
........\cpu_jtag_debug_module_wrapper.v
........\cpu_mult_cell.v
........\cpu_ociram_default_contents.mif
........\cpu_test_bench.v
........\dacontrol.v
........\.b\altsyncram_0t12.tdf
........\..\altsyncram_bp62.tdf
........\..\altsyncram_eh91.tdf
........\..\altsyncram_ifd1.tdf
........\..\altsyncram_jll1.tdf
........\..\altsyncram_khb1.tdf
........\..\altsyncram_lod1.tdf
........\..\altsyncram_rm12.tdf
........\..\altsyncram_shd1.tdf
........\..\altsyncram_stv1.tdf
........\..\altsyncram_thd1.tdf
........\..\altsyncram_ttv1.tdf
........\..\a_dpfifo_f721.tdf
........\..\a_fefifo_2cf.tdf
........\..\cntr_70j.tdf
........\..\cntr_7c7.tdf
........\..\cntr_rbb.tdf
........\..\dpram_h921.tdf
........\..\logic_util_heursitic.dat
........\..\mac_mult_kmm.tdf
........\..\mac_out_hsd.tdf
........\..\mult_4hm.tdf
........\..\mult_add_ovq2.tdf
........\..\prev_cmp_SOPC_PCI.qmsg
........\..\scfifo_8121.tdf
........\..\SOPC_PCI.cbx.xml
........\..\SOPC_PCI.cmp.rdb
........\..\SOPC_PCI.db_info
........\..\SOPC_PCI.hif
........\..\SOPC_PCI.map.hdb
........\..\SOPC_PCI.map.qmsg
........\..\SOPC_PCI.pre_map.hdb
........\..\SOPC_PCI.sld_design_entry.sci
........\..\SOPC_PCI.smart_action.txt
........\..\SOPC_PCI.tis_db_list.ddb
........\dc_tag_ram.mif
........\delay_reset_block.bdf
........\delay_reset_block.bsf
........\digital_in.v
........\digital_out.v
........\exchange_ram.hex
........\exchange_ram.v
........\Hard_Emulator.bsf
........\Hard_Emulator.ptf
........\Hard_Emulator.ptf.bak
........\Hard_Emulator.v
........\Hard_Emulator_generation_script
........\Hard_Emulator_log.txt
........\Hard_Emulator_setup_quartus.tcl
........\...............im\atail-f.pl
........\.................\dummy_file
........\.................\jtag_uart_0_input_mutex.dat
........\.................\jtag_uart_0_input_stream.dat
........\.................\jtag_uart_0_output_stream.dat
........\ic_tag_ram.mif
........\jtag_uart_0.v
........\led_pio.v
........\levelcontrol.v
........\myboard\class.ptf
........\.......\system\cmp_state.ini
........\.......\......\cpu_0.ocp
........\.......\......\cpu_0.v
........\.......\......\cpu_0_test_bench.v
........\.......\......\data_RAM.hex
........\.......\......\data_RAM.v
........\.......\......\.b\altsyncram_6791.tdf
........\.......\......\..\altsyncram_7q01.tdf
........\.......\......\..\altsyncram_an91.tdf
........\.......\......\..\altsyncram_bhc1.tdf
........\.......\......\..\altsyncram_dno1.tdf
........\.......\......\..\altsyncram_ju91.tdf
........\.......\......\..\altsyncram_nll1.tdf
........\.......\......\..\altsyncram_pr12.tdf
........\.......\......\..\altsyncram_q201.tdf
........\.......\......\..\altsyncram_ui01.tdf
........\.......\......\..\a_dpfifo_83p.tdf
........\.......\......\..\a_dpfifo_k721.tdf
........\.......\......\..\a_fefifo_7cf.tdf
........\.......\......\..\cntr_70j.tdf
........\.......\......\..\cntr_9c7.tdf
........\.......\......\..\cntr_df8.tdf
........\.......\......\..\cntr_rd8.tdf

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