DDR2 controller for sodi

ddr2_sodimm_x64_333MHz_hp2\ddr2_sodimm_x64_333MHz_hp2.qar
..........................\ddr2_sodimm_x64_333MHz_hp2.qarlog
..........................\.........................._restored\.sopc_builder\filters.xml
..........................\...................................\.............\install.ptf
..........................\...................................\.............\preferences.xml
..........................\...................................\altera\91sp1\ip\altera\sopc_builder_ip\altera_avalon_jtag_phy\altera_avalon_st_jtag_interface.sdc
..........................\...................................\......\.....\..\......\...............\......................\altera_avalon_st_jtag_interface_hw.tcl
..........................\...................................\......\.....\..\......\...............\..............packets_to_master\altera_avalon_packets_to_master_hw.tcl
..........................\...................................\......\.....\..\......\...............\..............sc_fifo\altera_avalon_sc_fifo_hw.tcl
..........................\...................................\......\.....\..\......\...............\...............t_bytes_to_packets\altera_avalon_st_bytes_to_packets_hw.tcl
..........................\...................................\......\.....\..\......\...............\.................idle_inserter\altera_avalon_st_idle_inserter_hw.tcl
..........................\...................................\......\.....\..\......\...............\......................remover\altera_avalon_st_idle_remover_hw.tcl
..........................\...................................\......\.....\..\......\...............\.................packets_to_bytes\altera_avalon_st_packets_to_bytes_hw.tcl
..........................\...................................\......\.....\..\......\...............\.......jtag_avalon_master\altera_jtag_avalon_master_hw.tcl
..........................\...................................\altera_avalon_half_rate_bridge.v
..........................\...................................\altera_avalon_half_rate_bridge_constraints.sdc
..........................\...................................\altera_avalon_packets_to_master.v
..........................\...................................\altera_avalon_packets_to_master_hw.tcl
..........................\...................................\altera_avalon_sc_fifo.v
..........................\...................................\altera_avalon_sc_fifo_hw.tcl
..........................\...................................\altera_avalon_st_bytes_to_packets.v
..........................\...................................\altera_avalon_st_bytes_to_packets_hw.tcl
..........................\...................................\altera_avalon_st_clock_crosser.v
..........................\...................................\altera_avalon_st_handshake_clock_crosser_hw.tcl
..........................\...................................\altera_avalon_st_idle_inserter.v
..........................\...................................\altera_avalon_st_idle_inserter_hw.tcl
..........................\...................................\altera_avalon_st_idle_remover.v
..........................\...................................\altera_avalon_st_idle_remover_hw.tcl
..........................\...................................\altera_avalon_st_jtag_interface.sdc
..........................\...................................\altera_avalon_st_jtag_interface.v
..........................\...................................\altera_avalon_st_jtag_interface_hw.tcl
..........................\...................................\altera_avalon_st_packets_to_bytes.v
..........................\...................................\altera_avalon_st_packets_to_bytes_hw.tcl
..........................\...................................\altera_avalon_st_pipeline_base.v
..........................\...................................\altera_avalon_st_pipeline_stage_hw.tcl
..........................\...................................\altera_jtag_avalon_master.v
........................

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