A simple multiple CPU,based on language verilog

simpleCPU\1.cr.mti
.........\1.mpf
.........\ALU.v
.........\ALU.v.bak
.........\c.cr.mti
.........\c.mpf
.........\.haipangzi\@a@l@u\verilog.asm
.........\..........\......\_primary.dat
.........\..........\......\_primary.vhd
.........\..........\.c@u\verilog.asm
.........\..........\....\_primary.dat
.........\..........\....\_primary.vhd
.........\..........\.g@r\verilog.asm
.........\..........\....\_primary.dat
.........\..........\....\_primary.vhd
.........\..........\.k@d_@c@p@u\verilog.asm
.........\..........\...........\_primary.dat
.........\..........\...........\_primary.vhd
.........\..........\.p@c\verilog.asm
.........\..........\....\_primary.dat
.........\..........\....\_primary.vhd
.........\..........\memory\verilog.asm
.........\..........\......\_primary.dat
.........\..........\......\_primary.vhd
.........\..........\.ux2\verilog.asm
.........\..........\....\_primary.dat
.........\..........\....\_primary.vhd
.........\..........\...4\verilog.asm
.........\..........\....\_primary.dat
.........\..........\....\_primary.vhd
.........\..........\register\verilog.asm
.........\..........\........\_primary.dat
.........\..........\........\_primary.vhd
.........\..........\........2\verilog.asm
.........\..........\.........\_primary.dat
.........\..........\.........\_primary.vhd
.........\..........\testbench\verilog.asm
.........\..........\.........\_primary.dat
.........\..........\.........\_primary.vhd
.........\..........\_info
.........\chaipangzi.cr.mti
.........\chaipangzi.mpf
.........\code.cr.mti
.........\code.mpf
.........\cu.v
.........\cu.v.bak
.........\GR.v
.........\GR.v.bak
.........\KD_cpu.cr.mti
.........\KD_cpu.mpf
.........\KD_CPU.v
.........\KD_CPU.v.bak
.........\mem.v
.........\mux-2.v
.........\mux4.v
.........\mux8.v
.........\pc.v
.........\pc.v.bak
.........\register.v
.........\register2.v
.........\test2.v
.........\test3.v
.........\test3.v.bak
.........\TESTBENCH.v
.........\TESTBENCH.v.bak
.........\transcript
.........\vish_stacktrace.vstf
.........\vsim.wlf
.........\work\@a@l@u\verilog.asm
.........\....\......\_primary.dat
.........\....\......\_primary.vhd
.........\....\.c@u\verilog.asm
.........\....\....\_primary.dat
.........\....\....\_primary.vhd
.........\....\.g@r\verilog.asm
.........\....\....\_primary.dat
.........\....\....\_primary.vhd
.........\....\.k@d_@c@p@u\verilog.asm
.........\....\...........\_primary.dat
.........\....\...........\_primary.vhd
.........\....\.p@c\verilog.asm
.........\....\....\_primary.dat
.........\....\....\_primary.vhd
.........\....\memory\verilog.asm
.........\....\......\_primary.dat
.........\....\......\_primary.vhd
.........\....\.ux2\verilog.asm
.........\....\....\_primary.dat
.........\....\....\_primary.vhd
.........\....\...4\verilog.asm
.........\....\....\_primary.dat
.........\....\....\_primary.vhd
.........\....\...8\verilog.asm
.........\....\....\_primary.dat
.........\....\....\_primary.vhd
.........\....\register\verilog.asm
.........\....\........\_primary.dat
.........\....\........\_primary.vhd
.........\....\........2\verilog.asm
.........\....\.........\_primary.dat

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