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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 378kb
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  • Author :xiao****
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Introduction - If you have any usage issues, please Google them yourself
The code to achieve the function of flash burning experiment
Packet file list
(Preview for download)
flash\db\flash_module.amm.cdb
.....\..\flash_module.asm.qmsg
.....\..\flash_module.asm.rdb
.....\..\flash_module.asm_labs.ddb
.....\..\flash_module.cbx.xml
.....\..\flash_module.cmp.bpm
.....\..\flash_module.cmp.cdb
.....\..\flash_module.cmp.hdb
.....\..\flash_module.cmp.kpt
.....\..\flash_module.cmp.logdb
.....\..\flash_module.cmp.rdb
.....\..\flash_module.cmp0.ddb
.....\..\flash_module.cmp1.ddb
.....\..\flash_module.cmp2.ddb
.....\..\flash_module.cmp_merge.kpt
.....\..\flash_module.db_info
.....\..\flash_module.eda.qmsg
.....\..\flash_module.fit.qmsg
.....\..\flash_module.hier_info
.....\..\flash_module.hif
.....\..\flash_module.idb.cdb
.....\..\flash_module.lpc.html
.....\..\flash_module.lpc.rdb
.....\..\flash_module.lpc.txt
.....\..\flash_module.map.bpm
.....\..\flash_module.map.cdb
.....\..\flash_module.map.hdb
.....\..\flash_module.map.kpt
.....\..\flash_module.map.logdb
.....\..\flash_module.map.qmsg
.....\..\flash_module.map_bb.cdb
.....\..\flash_module.map_bb.hdb
.....\..\flash_module.map_bb.logdb
.....\..\flash_module.pre_map.cdb
.....\..\flash_module.pre_map.hdb
.....\..\flash_module.rtlv.hdb
.....\..\flash_module.rtlv_sg.cdb
.....\..\flash_module.rtlv_sg_swap.cdb
.....\..\flash_module.sgdiff.cdb
.....\..\flash_module.sgdiff.hdb
.....\..\flash_module.sld_design_entry.sci
.....\..\flash_module.sld_design_entry_dsc.sci
.....\..\flash_module.smart_action.txt
.....\..\flash_module.sta.qmsg
.....\..\flash_module.sta.rdb
.....\..\flash_module.sta_cmp.8_slow.tdb
.....\..\flash_module.syn_hier_info
.....\..\flash_module.tis_db_list.ddb
.....\..\logic_util_heursitic.dat
.....\..\prev_cmp_flash_module.qmsg
.....\flash_module.asm.rpt
.....\flash_module.done
.....\flash_module.eda.rpt
.....\flash_module.fit.rpt
.....\flash_module.fit.smsg
.....\flash_module.fit.summary
.....\flash_module.flow.rpt
.....\flash_module.map.rpt
.....\flash_module.map.summary
.....\flash_module.pin
.....\flash_module.pof
.....\flash_module.qpf
.....\flash_module.qsf
.....\flash_module.sof
.....\flash_module.sta.rpt
.....\flash_module.sta.summary
.....\flash_module.v
.....\flash_module.v.bak
.....\flash_module_nativelink_simulation.rpt
.....\incremental_db\compiled_partitions\flash_module.db_info
.....\..............\...................\flash_module.root_partition.cmp.cdb
.....\..............\...................\flash_module.root_partition.cmp.dfp
.....\..............\...................\flash_module.root_partition.cmp.hdb
.....\..............\...................\flash_module.root_partition.cmp.kpt
.....\..............\...................\flash_module.root_partition.cmp.logdb
.....\..............\...................\flash_module.root_partition.cmp.rcfdb
.....\..............\...................\flash_module.root_partition.map.cdb
.....\..............\...................\flash_module.root_partition.map.dpi
.....\..............\...................\flash_module.root_partition.map.hbdb.cdb
.....\..............\...................\flash_module.root_partition.map.hbdb.hb_info
.....\..............\...................\flash_module.root_partition.map.hbdb.hdb
.....\..............\...................\flash_module.root_partition.map.hbdb.sig
.....\..............\...................\flash_module.root_partition.map.hdb
.....\..............\...................\flash_module.root_partition.map.kpt
.....\..............\README
.....\simulation\modelsim\flash_module.vt
.....\..........\........\flash_module.vt.bak
.....\..........\........\flash_module_run_msim_rtl_verilog.do
.....\..........\........\flash_module_run_msim_rtl_verilog.do.bak
.....\..........\........\flash_module_run_msim_rtl_verilog.do.bak1
.....\..........\........\flash_module_run_msim_rtl_verilog.do.bak10
.....\..........\........\flash_module_run_msim_rtl_verilog.do.bak11
.....\..........\........\flash_module_run_msim_rtl_verilog.do.bak2
.....\..........\........\flash_module_run_msim_rtl_verilog.do.bak3
.....\..........\........\flash_module_run_msim_rtl_verilog.do.bak4
.....\..........\........\flash_module_run_msim_rtl_verilog.do.bak5
.....\..........\........\flash_module_run_msim_rtl_ver
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