ofdm implementation in Verilog

TECH\220model.v
....\adder_24.v
....\altera_mf.v
....\c.ver
....\complex.v
....\contents.ver
....\contents_int.ver
....\cyc_rdadd.ver
....\de_int_add.ver
....\deinterleaver_addressrom.v
....\divider_ifft.v
....\fft_RAM.v
....\fft_twd1.v
....\fft_twd2.v
....\fft_twdrom1.ver
....\fft_twdrom2.ver
....\fifo.v
....\fifo_register.v
....\fifo_rsdec.v
....\lpm.v
....\lpm_divide.v
....\my_divider.v
....\PLL.v
....\RAM_64x48.v
....\recout_fifo.v
....\ReedSolomon_decoder
....\...................\altera_mf
....\...................\.........\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s
....\...................\.........\..........................................\_primary.dat
....\...................\.........\..........................................\_primary.vhd
....\...................\.........\..........................................\verilog.asm
....\...................\.........\@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n
....\...................\.........\...............................................\_primary.dat
....\...................\.........\...............................................\_primary.vhd
....\...................\.........\...............................................\verilog.asm
....\...................\.........\@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n
....\...................\.........\...........................................................\_primary.dat
....\...................\.........\...........................................................\_primary.vhd
....\...................\.........\...........................................................\verilog.asm
....\...................\.........\@m@f_cycloneiii_pll
....\...................\.........\...................\_primary.dat
....\...................\.........\...................\_primary.vhd
....\...................\.........\...................\verilog.asm
....\...................\.........\@m@f_pll_reg
....\...................\.........\............\_primary.dat
....\...................\.........\............\_primary.vhd
....\...................\.........\............\verilog.asm
....\...................\.........\@m@f_ram7x20_syn
....\...................\.........\................\_primary.dat
....\...................\.........\................\_primary.vhd
....\...................\.........\................\verilog.asm
....\...................\.........\@m@f_stratix_pll
....\...................\.........\................\_primary.dat
....\...................\.........\................\_primary.vhd
....\...................\.........\................\verilog.asm
....\...................\.........\@m@f_stratixii_pll
....\...................\.........\..................\_primary.dat
....\...................\.........\..................\_primary.vhd
....\...................\.........\..................\verilog.asm
....\...................\.........\@m@f_stratixiii_pll
....\...................\.........\...................\_primary.dat
....\...................\.........\...................\_primary.vhd
....\...................\.........\...................\verilog.asm
....\...................\.........\_info
....\...................\.........\a_graycounter
....\...................\.........\.............\_primary.dat
....\...................\.........\.............\_primary.vhd
....\...................\.........\.............\verilog.asm
....\...................\.........\alt3pram
....\...................\.........\........\_primary.dat
....\...................\.........\........\_primary.vhd
....\...................\.........\........\verilog.asm
....\...................\.........\altaccumulate
....\...................\.........\.............\_primary.dat
....\...................\.........\.............\_primary.vhd
....\...................\.........\.............\verilog.asm
....\...................\.........\altcam
....\...................\.........\......\_primary.dat
....\...................\.........\......\_primary.vhd
....\...................\.........\......\verilog.asm
....\...................\.........\al

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