STM32 FSMC interface code and specification

hssdrc
......\tags
......\branches
......\trunk
......\.....\doc
......\.....\...\hssdrc_design_document_rev10.odt
......\.....\...\hssdrc_design_document.pdf
......\.....\testbench
......\.....\.........\hssdrc_driver_class.sv
......\.....\.........\tb_prog.sv
......\.....\.........\hssrdc_bandwidth_monitor_class.sv
......\.....\.........\hssrdc_driver_cbs_class.sv
......\.....\.........\hssrdc_scoreboard_class.sv
......\.....\.........\sdram_agent_class.sv
......\.....\.........\sdram_interpretator.sv
......\.....\.........\message_class.sv
......\.....\.........\tb_top.sv
......\.....\.........\sdram_tread_class.sv
......\.....\.........\sdram_transaction_class.sv
......\.....\sim
......\.....\...\compile.do
......\.....\...\sim.do
......\.....\include
......\.....\.......\tb_define.svh
......\.....\.......\hssdrc_timescale.vh
......\.....\.......\hssdrc_tb_sys_if.vh
......\.....\.......\hssdrc_define.vh
......\.....\.......\hssdrc_timing.vh
......\.....\core
......\.....\....\test.v
......\.....\....\mt48lc2m32b2.v
......\.....\rtl
......\.....\...\hssdrc_access_manager.v
......\.....\...\hssdrc_decoder_state.v
......\.....\...\hssdrc_addr_path_p1.v
......\.....\...\hssdrc_addr_path.v
......\.....\...\hssdrc_refr_counter.v
......\.....\...\hssdrc_mux.v
......\.....\...\hssdrc_arbiter_in.v
......\.....\...\hssdrc_data_path.v
......\.....\...\hssdrc_data_path_p1.v
......\.....\...\hssdrc_ba_map.v
......\.....\...\hssdrc_arbiter_out.v
......\.....\...\hssdrc_decoder.v
......\.....\...\hssdrc_top.v
......\.....\...\hssdrc_init_state.v
......\.....\readme.txt
......\web_uploads

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