The Verilog language implementation the I2C master controller example, testing program

i2c_controller
..............\chart
..............\.....\Thumbs.db
..............\.....\图7-11.bmp
..............\.....\图7-12.bmp
..............\.....\图7-14.bmp
..............\.....\图7-15.bmp
..............\.....\图7-16.bmp
..............\.....\图7-17.bmp
..............\.....\图7-18.bmp
..............\.....\图7-21.bmp
..............\.....\图7-22.bmp
..............\.....\图7-23.bmp
..............\i2c_controller.cr.mti
..............\i2c_controller.mpf
..............\i2c_master_bit_ctrl.v
..............\i2c_master_byte_ctrl.v
..............\i2c_master_defines.v
..............\i2c_master_top.v
..............\i2c_slave_model.v
..............\timescale.v
..............\transcript
..............\tst_bench_top.v
..............\vsim.wlf
..............\wave
..............\....\i2c_master_bit_ctrl.bmp
..............\....\i2c_master_byte_ctrl.bmp
..............\....\i2c_master_top.bmp
..............\....\i2c_slave_model.bmp
..............\....\Thumbs.db
..............\....\tst_bench_top.bmp
..............\....\wb_master_model.bmp
..............\wb_master_model.v
..............\work
..............\....\delay
..............\....\.....\verilog.asm
..............\....\.....\_primary.dat
..............\....\.....\_primary.vhd
..............\....\i2c_master_bit_ctrl
..............\....\...................\verilog.asm
..............\....\...................\_primary.dat
..............\....\...................\_primary.vhd
..............\....\i2c_master_byte_ctrl
..............\....\....................\verilog.asm
..............\....\....................\_primary.dat
..............\....\....................\_primary.vhd
..............\....\i2c_master_top
..............\....\..............\verilog.asm
..............\....\..............\_primary.dat
..............\....\..............\_primary.vhd
..............\....\i2c_slave_model
..............\....\...............\verilog.asm
..............\....\...............\_primary.dat
..............\....\...............\_primary.vhd
..............\....\tst_bench_top
..............\....\.............\verilog.asm
..............\....\.............\_primary.dat
..............\....\.............\_primary.vhd
..............\....\wb_master_model
..............\....\...............\verilog.asm
..............\....\...............\_primary.dat
..............\....\...............\_primary.vhd
..............\....\_info

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